PLL Phase Detector and VCO Layout for Low-Spur Clock Signals
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Solution Overview
Problem
Conventional phase locked loop (PLL) circuits face issues with parasitic capacitance causing frequency shifts, spurs in reference signals leading to interference, and reference clock feedthrough, which hinder the generation of high-speed and low-noise clock signals.
Innovation Solution
A PLL system comprising a phase-frequency detector, loop filter, voltage controlled oscillator, and 3-stage frequency divider, with a voltage controlled oscillator using a transmission line pair, cross-coupled transistor pair, and varactor to generate a VCO output signal, and a phase-frequency detector employing single sideband mixers to suppress reference spurs and reduce noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional charge pump PLL is used with pulse-width comparison in phase detector, then phase and frequency detection is achieved, but reference spurs cause interference to adjacent transmission channels
Solution Approach 1:
The patent extracts and eliminates the harmful pulse generation mechanism from the conventional charge pump PLL by replacing it with a current-mode logic phase detector that uses analog voltage comparison instead of pulse-width comparison, thereby removing the source of reference spurs while maintaining phase and frequency detection functionality
Solution Approach 2:
The patent introduces an analog phase detector using current-mode logic as an intermediary component between the reference signal and charge pump circuit, which mediates the phase detection process through continuous voltage comparison rather than discrete pulse comparison, thus suppressing reference feedthrough and spurs
2Speed
If miniaturized CMOS devices are used to achieve higher operating speeds, then circuit integration and power consumption are improved, but parasitic capacitance causes frequency shift of signals
Solution Approach 1:
The patent replaces traditional mechanical or conventional electronic frequency division and phase detection mechanisms with a fully integrated current-mode logic system that uses transconductance amplifiers and analog voltage comparison, eliminating the harmful effects of parasitic capacitance associated with conventional switching-based approaches
Solution Approach 2:
The patent changes the operating parameters of the PLL by using continuous analog voltage signals instead of discrete digital pulses for phase detection, and by employing current-mode logic throughout the signal path, which fundamentally alters how the circuit responds to parasitic capacitance and maintains frequency stability at high speeds
3Measurement precision
If conventional phase detector with pulse generation is used, then phase error detection is achieved, but control line ripple is never entirely removed
Solution Approach 1:
The patent extracts and removes the pulse generation mechanism from the phase detector, replacing it with a continuous analog voltage comparison approach using current-mode logic, which eliminates the abrupt changes in control voltage that cause ripple while maintaining accurate phase error detection through proportional voltage output
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the production of a clock signal with low jitter and a wide operating range, effectively addressing frequency shift and interference issues, resulting in a high-speed and low-noise clock signal generation.
Implementation Method 1
The varactor, coupled to the open-circuited ends of the transmission line pair, adjusts the initial VCO wavelength of the VCO output signal according to a control voltage to a final VCO wavelength
Implementation Method 2
The cross-coupled transistor pair is coupled to one third of the length of the transmission line pair from the short circuited end pair
Implementation Method 3
Phase-frequency detector 10 compares reference signal CKin with a feedback signal to determine a phase and frequency error therebetween
Data Source
AI summary
A phase locked loop, voltage controlled oscillator, and phase-frequency detector are provided. The phase locked loop comprises a phase-frequency detector (PFD), a loop filter (LF), a voltage controlled oscillator (VCO), and a 3-stage frequency divider. The PFD receives a reference signal and a feedback signal to determine phase and frequency errors. The LF), coupled to the phase-frequency detector, filters the phase and frequency errors to generate a control voltage. The VCO, coupled to the loop filter, generates a VCO output signal according to the control voltage. The 3-stage frequency divider, coupled to the voltage controlled oscillator, divides the frequency of the VCO output signal 3 times to generate the feedback signal.