PLL Reconfiguration Using Calibrated LUTs for Lock Range Selection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing phase-locked loop (PLL) calibration methods require large tables of configuration parameters, leading to inefficient memory consumption and processing, especially for PLLs operating over smaller frequency ranges with multiple voltage-controlled oscillators (VCOs) and varying environmental conditions.
Innovation Solution
The implementation of a calibrated lookup table (LUT) that stores only the combinations of VCOs, tuning parameters, and loop divider values that achieve a locked state, allowing for efficient reconfiguration by selecting optimal entries based on requested settings, reducing the table size and improving processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a comprehensive table of configuration parameters is used to support all possible loop divider values and VCO combinations, then the PLL can achieve wide frequency range coverage, but memory consumption and table search processing become inefficient for smaller frequency ranges
Solution Approach 1:
The patent divides the comprehensive configuration table into multiple smaller lookup tables, each dedicated to a specific VCO and its associated loop divider values. This segmentation allows the system to only access the relevant subset of parameters needed for the currently active VCO, rather than storing and searching through all possible configurations across all VCOs. The segmented approach maintains full frequency range coverage while reducing memory consumption for any given operating mode.
Solution Approach 2:
The patent implements dynamic selection of lookup tables based on the active VCO and operating conditions. Instead of using a static comprehensive table, the system dynamically determines which lookup table to access based on the currently selected VCO and desired frequency range. This dynamic approach ensures that only the necessary configuration parameters are loaded into memory and processed, optimizing both memory usage and search efficiency while maintaining adaptability across the full frequency spectrum.
2Adaptability or versatility
If a comprehensive table of configuration parameters is used to support all possible loop divider values and VCO combinations, then the PLL can achieve wide frequency range coverage, but table search processing time increases
Solution Approach 1:
By segmenting the configuration data into separate lookup tables for each VCO, the patent dramatically reduces the search space. When a frequency configuration is needed, the system only searches within the specific lookup table corresponding to the active VCO, rather than searching through a comprehensive table containing all possible VCO and loop divider combinations. This segmentation reduces processing time from O(N) where N is the total number of all possible configurations to O(M) where M is the much smaller number of configurations for a single VCO.
Solution Approach 2:
The patent performs preliminary organization of configuration parameters into VCO-specific lookup tables during system initialization or calibration. This preliminary action pre-groups the configuration data so that when the PLL needs to be configured, the search is already constrained to a small, relevant subset. The preliminary organization eliminates the need for extensive searching through all possible configurations during operation, significantly reducing table search processing time while maintaining full frequency range coverage capability.
3Reliability
If calibration parameters are stored for all possible VCO and loop divider combinations, then complete frequency coverage is achieved, but the complexity of the calibration system increases
Solution Approach 1:
The patent reduces calibration system complexity by segmenting the calibration process into VCO-specific calibration routines. Instead of calibrating and storing parameters for all possible VCO and loop divider combinations in a single comprehensive system, the calibration is performed separately for each VCO, with results stored in dedicated lookup tables. This segmentation simplifies the calibration system architecture, making it more manageable and less complex while maintaining complete frequency coverage through the combined set of VCO-specific tables.
Solution Approach 2:
The patent extracts and isolates the calibration parameters for each VCO into separate lookup tables, removing the need to manage a single large complex calibration system. By taking out the calibration data for each VCO and storing it independently, the system reduces overall complexity. Each lookup table contains only the calibration parameters relevant to its specific VCO, eliminating the need to process and manage the entire set of all possible combinations in a single complex structure.
Data Source
AI summary
Techniques are provided for phase-locked loop (PLL) configuration, based on a calibrated lookup table (LUT). A methodology implementing the techniques according to an embodiment includes selecting one of a number of voltage controlled oscillators (VCOs) of the PLL, and selecting a tuning parameter to control the VCO. The method further includes testing the PLL, using multiple loop divider values, to determine a minimum and maximum value that define the lower and upper bounds of a range of loop divider values for which the PLL achieves a locked state while using the selected VCO and tuning parameter. The method further includes storing PLL configuration parameters to an entry in the configuration LUT, the PLL configuration parameters to include an identification of the selected VCO, the selected tuning parameter, the minimum loop divider value, and the maximum loop divider value. The method iterates using additional combinations of selected VCOs and tuning parameters.