PLL Realignment Circuit Using Matched Gates to Prevent Lock Breaks
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Solution Overview
Problem
Phase locked loops (PLLs) used in high-speed clock generation often exhibit anomalous behavior due to phase noise and spurious signals, leading to suboptimal output from voltage-controlled oscillators (VCOs) over time, which can break the locking condition and require accurate clock realignment.
Innovation Solution
Implementing a realignment path with charge pump-based PLLs that includes matching skew mitigation circuitry using identical logic gates to generate accurately timed clock realignment signals, ensuring proper alignment with the VCO and PLL state without breaking the locked condition, and using a pulse generator with controllable pulse width to maintain optimal operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a PLL is used to lock the phase and frequency of a VCO to a reference device, then the phase and frequency stability is improved, but phase noise and spurious signals cause anomalous behavior and lock breaks over time
Solution Approach 1:
The patent applies preliminary action by implementing a realignment path that proactively detects phase and frequency deviations before they cause lock breaks. The system continuously monitors the locked condition and pre-corrects anomalies through realignment signals, preventing the harmful effects of phase noise and spurious signals from disrupting operation.
Solution Approach 2:
The patent implements feedback mechanisms where the PLL continuously compares the VCO output with the reference device and adjusts the control voltage accordingly. Additionally, a realignment feedback path monitors for lock condition degradation and triggers corrective realignment actions, creating multiple feedback loops that work together to maintain stability despite phase noise and spurious signals.
2Measurement precision
If clock realignment signals are generated to correct phase and frequency deviations, then alignment accuracy is improved, but timing skew between realignment path and VCO can break the locked condition
Solution Approach 1:
The patent addresses timing skew by introducing asymmetric delay compensation elements in the realignment path. Different delay compensation is applied to UP and DN realignment signals based on their specific timing requirements, ensuring that both signals arrive at the D flip-flop simultaneously despite traveling through different logic paths. This asymmetric compensation maintains the locked condition while achieving precise realignment.
Solution Approach 2:
The patent uses delay compensation logic as an intermediary element between the realignment signal generation and the D flip-flop. This intermediary component introduces controlled delays to synchronize the UP and DN realignment signals, mediating the timing difference caused by asymmetric logic paths and preventing lock breaks.
3Manufacturing precision
If matching skew mitigation circuitry with identical logic gates is used, then timing skew is reduced, but device complexity increases
Solution Approach 1:
The patent applies homogeneity by using identical logic gates (such as matching AND gates or OR gates) for both UP and DN realignment paths. This homogeneous design ensures that both signals experience the same propagation delays and logic transitions, automatically compensating for skew without requiring complex individual calibration for each path. The symmetry in gate selection simplifies the overall design while achieving precise timing matching.
Data Source
AI summary
Systems and methods are provided for a phase locked loop. A phase/frequency detector is configured to receive a reference signal and a feedback signal. A charge pump is configured to receive outputs from the phase/frequency detector and to generate pulses. An oscillator is configured to generate an output waveform based on the charge pump pulses. A realignment path is configured to generate a clock realignment signal that is provided to the oscillator based on the outputs from the phase/frequency detector.