PLL Frequency Synthesizer With Mixed Divider Feedback
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Solution Overview
Problem
Conventional frequency synthesizers for mobile telephones require multiple reference signal oscillators, leading to increased cost and complexity due to large-scale circuitry and complicated arrangements.
Innovation Solution
A frequency synthesizer design utilizing first and second frequency dividers for common input clock signal division, combined with a frequency mixer in a feedback loop within a PLL circuit, allowing for both integral and fractional frequency division outputs from a single reference oscillator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple reference signal oscillators are used to generate different frequency outputs, then frequency versatility is improved, but device complexity and cost increase
Solution Approach 1:
The patent implements a single reference oscillator that serves multiple frequency generation functions through a combination of integer frequency dividers and fractional frequency dividers. The fractional frequency divider dynamically adjusts division ratios to generate multiple output frequencies (including GPS L1, L2, L5 and mobile communication frequencies) from one reference source, eliminating the need for separate oscillators for each frequency band while maintaining frequency versatility.
Solution Approach 2:
The patent merges integer frequency division and fractional frequency division functions into a unified frequency synthesis architecture. The fractional frequency divider combines the functionalities of multiple separate dividers and mixers that would traditionally be required, consolidating the frequency generation system into a more integrated structure that reduces overall device complexity while maintaining the ability to generate multiple frequency outputs.
2Adaptability or versatility
If multiple frequency synthesizer units are used to achieve different frequency bands, then frequency coverage is improved, but device complexity increases
Solution Approach 1:
The frequency synthesis unit is designed to perform multiple frequency band generation functions through a single integrated structure. By using a fractional frequency divider that can dynamically change division ratios based on control signals, the system generates frequencies for GPS bands (L1, L2, L5) and mobile communication bands from one synthesizer unit, eliminating the need for separate synthesizer units for each frequency band.
Solution Approach 2:
The patent employs dynamic frequency division ratios in the fractional frequency divider, allowing the system to adaptively generate different output frequencies by changing the division ratio in response to control signals. This dynamic capability enables a single frequency synthesizer unit to cover multiple frequency bands that would traditionally require multiple static synthesizer units, thereby reducing device complexity while maintaining comprehensive frequency coverage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design simplifies circuitry and reduces costs by generating multiple frequency outputs from a single reference oscillator, achieving both integral and fractional frequency divisions with reduced circuit complexity and spurious noise suppression.
Implementation Method 1
a frequency mixer for mixing output signals of the first and second frequency dividers
Data Source
AI summary
A frequency synthesizer includes first and second frequency dividers for receiving and frequency-dividing a signal generated by a voltage-controlled oscillator, a frequency mixer for mixing output signals of the first and second frequency dividers, and a third frequency divider for receiving and frequency-dividing a signal having one frequency of two frequencies that are output by the frequency mixer. The first, second third and frequency dividers and the frequency mixer are provided in a feedback loop within a PLL circuit between the voltage-controlled oscillator and the phase comparator. The phase comparator has a first input terminal to which a signal to which a signal that is output by the third frequency divider is input and a second input terminal to which a reference clock signal that is output by a reference signal generator is input. A loop filter supplies the voltage-controlled oscillator with a voltage that is based upon result of the phase comparison by a phase comparator. The voltage-controlled oscillator supplies the first and second frequency dividers with a signal that oscillates at a frequency corresponding to the voltage input to the oscillator.