Dual-Reference PLL Clocking for Low-Phase-Noise RF LO Synthesis
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Solution Overview
Problem
Modern multi-carrier RF systems face challenges in creating low Phase Noise LO clock sources with wide tuning ranges and fine frequency resolution, as existing technologies struggle to integrate low noise clock generators due to high Phase Noise from network timing references and manufacturing tolerances of MEMS and BAW devices.
Innovation Solution
The integration of Integer-N and Fractional-N PLLs with a mixer that combines high Phase Noise and low Phase Noise clock signals, using MEMS or BAW resonators, to generate low Phase Noise LO clocks suitable for RF systems, allowing for flexible frequency tuning and reduced noise amplification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If network timing references are used for frequency accuracy, then frequency resolution is improved, but Phase Noise increases
Solution Approach 1:
The system segments the clock generation function into two separate reference inputs: one dedicated to frequency accuracy and another to Phase Noise performance. This allows each reference to be optimized for its specific function rather than requiring a single reference to excel at both.
Solution Approach 2:
The patent introduces an intermediary mechanism (the dual-reference architecture with separate processing paths) that mediates between the conflicting requirements of frequency accuracy and Phase Noise performance, allowing both to be satisfied simultaneously through controlled combination of signals from both references.
2Adaptability or versatility
If wide tuning range is implemented, then adaptability is improved, but frequency resolution deteriorates
Solution Approach 1:
The frequency tuning function is segmented into coarse tuning (providing wide range) and fine tuning (providing high resolution) components. The coarse tuning establishes the base frequency from the first reference, while the fine tuning mechanism adjusts with high precision using the second reference, allowing both wide range and high resolution to coexist.
Solution Approach 2:
The system adds an additional dimension to frequency control by introducing a second reference input that operates independently. This creates a two-dimensional frequency control space where one dimension provides range and the other provides resolution, effectively resolving the trade-off between tuning range and frequency resolution.
3Manufacturing precision
If Integer-N and Fractional-N PLLs are integrated, then device complexity increases, but manufacturing precision is improved
Solution Approach 1:
The patent merges Integer-N and Fractional-N PLL architectures into a unified dual-reference system, combining their respective strengths for frequency accuracy and Phase Noise performance. This integration achieves high manufacturing precision through the complementary operation of both PLL types while managing complexity through shared components and coordinated control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides low Phase Noise LO clocks with sufficient tuning range and frequency resolution for multi-carrier RF systems, integrating components in a single package and reducing noise, thus enhancing the Signal-to-Noise Ratio and frequency accuracy.
Implementation Method 1
with a mixer, combining the modified clock signal with the second clock signal to obtain a signal having a frequency sum component and a frequency difference component
Implementation Method 2
the FNPLL circuit being configured to have a FNPLL bandwidth that filters out the first clock signal Phase Noise
Implementation Method 3
the INPLL circuit having an INPLL bandwidth that filters out Phase Noise generated by the second VCO circuitry
Implementation Method 4
using MEMS or BAW resonators, to generate low Phase Noise LO clocks
Data Source
AI summary
A number of methods and clock generator units are disclosed to produce low Phase Noise clocks for use in Radio Frequency systems. The methods and clock generator units all use two reference clocks: a frequency-accurate reference that has comparatively high Phase Noise, and a frequency-inaccurate reference such as that from a BAW or MEMS clock source that has comparatively low Phase Noise. By combining multiple Phase-Locked Loops and a mixer, it is possible to produce flexible output frequencies whose frequency accuracy is derived from the first reference clock but whose Phase Noise level is derived from the second reference clock, all in a readily-integrated and relatively low-cost system.