PLL Direct Modulation Calibration for Accurate OQPSK Signaling
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Solution Overview
Problem
High frequency signal processing devices, particularly those using PLL circuits for ZigBee communication, face challenges in reducing power consumption and circuit area while maintaining modulation accuracy, due to the complexity of IQ quadrature modulation systems and the need for calibration to achieve wide-band communications.
Innovation Solution
A high frequency signal processing device incorporating a two-point modulation system with a digital calibration circuit that uses a divider, analog loop control, and a calibration controller to search for optimal modulation codes, reducing circuit complexity and power consumption by leveraging digital calibration for accurate frequency control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an IQ quadrature modulation system is used to achieve OQPSK modulation, then modulation accuracy and communication stability are improved, but circuit area and power consumption increase due to the complexity of requiring multiple circuits (two DACs, two LPFs, two MIXes, etc.)
Solution Approach 1:
The patent merges the functions of multiple separate circuits (I-channel and Q-channel modulation circuits) into a single PLL-based direct modulation circuit. This consolidation achieves OQPSK modulation functionality while significantly reducing circuit area and component count, directly resolving the contradiction between communication reliability and device complexity.
Solution Approach 2:
The PLL circuit is designed to perform multiple functions: frequency synthesis, phase modulation, and direct OQPSK modulation. By making the PLL circuit multi-functional, the patent eliminates the need for separate dedicated modulation circuits, thereby reducing overall system complexity while maintaining modulation accuracy and communication stability.
2Reliability
If an IQ quadrature modulation system is used to achieve OQPSK modulation, then modulation accuracy and communication stability are improved, but power consumption increases due to the complexity of requiring multiple circuits
Solution Approach 1:
The patent merges the functions of multiple separate circuits (I-channel and Q-channel modulation circuits) into a single PLL-based direct modulation circuit. This consolidation achieves OQPSK modulation functionality while significantly reducing circuit area and component count, directly resolving the contradiction between communication reliability and device complexity.
Solution Approach 2:
The PLL circuit is designed to perform multiple functions: frequency synthesis, phase modulation, and direct OQPSK modulation. By making the PLL circuit multi-functional, the patent eliminates the need for separate dedicated modulation circuits, thereby reducing overall system complexity while maintaining modulation accuracy and communication stability.
3Device complexity
If a PLL direct modulation system is used to reduce circuit area and power consumption, then device complexity and energy use are reduced, but modulation accuracy may deteriorate without proper calibration
Solution Approach 1:
The patent implements a calibration circuit that performs preliminary calibration of the PLL modulation parameters before normal operation. By pre-adjusting the modulation index and frequency offsets to optimal values, the system ensures high modulation accuracy is achieved despite the simplified circuit architecture, thus resolving the contradiction between device complexity and measurement precision.
Solution Approach 2:
The calibration circuit uses feedback mechanisms to measure and adjust PLL modulation parameters. By continuously monitoring modulation accuracy and adjusting parameters accordingly, the system maintains high precision in the simplified PLL direct modulation architecture, resolving the trade-off between circuit simplicity and modulation accuracy.
4Reliability
If calibration is performed to achieve wide-band communications with PLL direct modulation, then communication bandwidth and reliability are improved, but power consumption and circuit complexity increase due to calibration circuit requirements
Solution Approach 1:
The patent implements a calibration circuit that performs preliminary calibration of the PLL modulation parameters before normal operation. By pre-adjusting the modulation index and frequency offsets to optimal values, the system ensures high modulation accuracy is achieved despite the simplified circuit architecture, thus resolving the contradiction between device complexity and measurement precision.
Solution Approach 2:
The calibration circuit uses feedback mechanisms to measure and adjust PLL modulation parameters. By continuously monitoring modulation accuracy and adjusting parameters accordingly, the system maintains high precision in the simplified PLL direct modulation architecture, resolving the trade-off between circuit simplicity and modulation accuracy.
Data Source
AI summary
A high frequency signal processing device is capable of carrying out high-accuracy modulation by a PLL circuit. A digital loop is configured in addition to an analog loop having, for example, a phase frequency detector, a charge pump circuit, and a loop filter. A digital calibration circuit is provided which searches for the optimal code set to a capacitor bank upon frequency modulation. Upon the search for the optimal code, a calibration controller first sets a division ratio based on a center frequency to a divider and determines the value of a voltage control signal using the analog loop. Then, the loop filter holds the value of the voltage control signal therein, and a division ratio corresponding to a “center frequency+modulated portion” is set to the divider, thereby operating the digital loop. The optimal code is obtained by a convergent value of the digital loop.