PLL Synchronization for Multi-Tile Power Converter Switching Frequencies
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Solution Overview
Problem
Synchronizing multiple power converters operating at high switching frequencies in integrated circuits is challenging, especially in portable electronics where component sizes need to be reduced, and existing technologies face difficulties in achieving synchronized switching frequencies without external clock synchronization.
Innovation Solution
A phase locked loop is used to synchronize the switching frequency of high-frequency switching power converters to a master clock signal, allowing multiple tiles of switching power converters to operate at integer multiples of the clock frequency, eliminating the need for an internal oscillator to determine switching frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple power converters operate at high switching frequencies to reduce component size, then component size is reduced, but synchronization difficulty increases
Solution Approach 1:
The patent merges multiple power converter operations under a unified clock synchronization system. A master clock signal is distributed to all power converters through a common clock distribution network, ensuring that all converters operate at synchronized high frequencies. This approach allows component size reduction while maintaining synchronization through centralized clock management.
2Reliability
If conventional feedback amplifiers and controllers are used to regulate output voltage, then voltage regulation is achieved, but switching frequency is limited due to delays
Solution Approach 1:
The patent applies preliminary action by using a phase-locked loop (PLL) to pre-synchronize the switching frequencies of all power converters before they operate. The PLL circuit adjusts the switching frequency of each converter to match integer multiples of a master clock frequency, ensuring synchronization is established in advance. This eliminates the need for real-time delay compensation in feedback amplifiers, enabling higher switching frequencies while maintaining voltage regulation.
3Speed
If hysteretic converters are used to achieve higher frequency operation, then switching frequency increases, but external clock synchronization becomes difficult
Solution Approach 1:
The patent implements feedback by using a phase-locked loop (PLL) circuit that continuously monitors and adjusts the switching frequency of hysteretic converters. The PLL compares the converter's switching frequency with a master clock signal and generates corrective feedback to synchronize the converter's operation. This feedback mechanism enables hysteretic converters to operate at high frequencies while maintaining precise synchronization with external clock signals.
Data Source
AI summary
A phase locked loop is used to synchronize the switching frequency of a high frequency switching power converter to a clock signal. A switching power converter integrated circuit is a tile-based power management unit and includes an oscillator and multiple tiles of switching power converters. The oscillator generates a clock signal having a clock frequency. A first switching power converter includes a switch and a phase locked loop and switches at a first frequency. The switch has a gate that receives a gate signal. The phase locked loop synchronizes the first frequency to a first integer multiple of the clock frequency. A second switching power converter switches at a second frequency that is a second integer multiple of the clock frequency. The first frequency is synchronized to a multiple of the clock frequency when a second edge of the gate signal coincides with a first edge of the clock signal.