PLL Feedback Architecture Using Multiple Error Determiners
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Solution Overview
Problem
Phase-locked loops (PLLs) in electronic devices face challenges in producing a stable and clean synthesized frequency, particularly at millimeter wave frequencies, due to noise components injected by frequency dividers, which can violate phase noise constraints in next-generation wireless communication standards like 5G NR.
Innovation Solution
The implementation of multiple error determiners within the PLL, each comprising a phase-frequency detector and a charge pump, or a time-to-digital converter, to combine and reduce noise components, thereby averaging them and minimizing phase noise in the output frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a frequency divider is used in the PLL feedback path, then the output frequency can be controlled by dividing the VCO frequency, but noise components are injected into the feedback loop which increases phase noise in the output signal
Solution Approach 1:
The single error determiner is segmented into multiple parallel error determiners (first, second, and third error determiners). Each error determiner independently processes the feedback signal with its own phase-frequency detector and charge pump, allowing the noise components from the frequency divider to be averaged across multiple independent detection paths, thereby reducing the overall phase noise in the output signal.
2Object-generated harmful factors
If multiple error determiners are implemented in parallel, then phase noise is reduced through averaging, but the device complexity increases due to additional components
Solution Approach 1:
Multiple error determiners are merged into a unified PLL architecture where their output signals are combined and fed into a common loop filter. This merging approach allows the benefits of noise averaging from multiple independent detection paths while sharing common components such as the VCO, frequency divider, and loop filter, thereby reducing the overall complexity increase compared to having completely separate PLL circuits.
Data Source
AI summary
An apparatus is disclosed that implements a phase-locked loop (PLL) that uses multiple error determiners as part of a feedback loop. In an example aspect, an apparatus for generating a frequency includes a PLL. The PLL includes a loop filter, a voltage-controlled oscillator (VCO), a frequency divider, and multiple error determiners. The loop filter includes a filter input node and a filter output node. The VCO includes a VCO input node and a VCO output node. The VCO input node is coupled to the filter output node. The frequency divider includes a divider input node and multiple divider output nodes. The divider input node is coupled to the VCO output node. The multiple error determiners are coupled between the multiple divider output nodes and the filter input node.