PLL Frequency Synthesizer Noise Correction Using Phase Shifting
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Solution Overview
Problem
Existing frequency synthesizers face challenges with high phase noise and spurious signals due to the use of high division ratios, which are exacerbated by switching between different PLL loops, leading to PLL instability and false locks.
Innovation Solution
A noise-corrected phase-locked loop frequency synthesizer design that incorporates a phase shifter driven by noise detecting sensors to reduce phase noise, using a separate phase-lock mechanism independent of the divider-by-N PLL path, and optimizing loop filters for improved stability and noise reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high division ratios are used in the frequency divider, then frequency resolution is improved, but phase noise increases significantly
Solution Approach 1:
The patent divides the single high-ratio frequency division into multiple lower-ratio division stages. Instead of using one frequency divider with a high division ratio N, the system uses multiple frequency dividers with lower division ratios (e.g., N1, N2, N3 where N1×N2×N3 = N). This segmentation reduces the phase noise contribution from each divider while achieving the same overall frequency resolution, as phase noise accumulates additively rather than multiplicatively across stages.
Solution Approach 2:
The patent introduces intermediate frequency stages as mediators between the VCO and the final divided frequency. These intermediate stages include additional VCOs and frequency dividers that break up the direct high-ratio division path. The intermediary stages allow for better noise management by distributing the division function across multiple components with optimized individual division ratios.
2Adaptability or versatility
If switching between different PLL loops is performed rapidly, then adaptability is improved, but PLL stability deteriorates causing false locks
Solution Approach 1:
The patent implements dynamic control of the frequency synthesis process by allowing the system to operate in different modes depending on the required frequency. The system can dynamically select between direct synthesis paths and divided synthesis paths, and can adjust division ratios on-the-fly. This dynamic adaptability allows rapid frequency switching while maintaining stability through controlled transitions rather than abrupt switching between fixed PLL loops.
Solution Approach 2:
The patent changes operational parameters (division ratios, feedback paths) dynamically based on the desired output frequency. Instead of switching between completely different PLL loops, the system modifies parameters within a unified PLL architecture, such as changing the division ratio N or selecting different feedback divider configurations. This parameter-based adaptation maintains PLL stability while achieving frequency versatility.
Data Source
AI summary
An improved noise-corrected phase-locked loop frequency synthesizer configured to reduce noise, such as phase noise and spurious signals, without the use of switching circuits. The synthesizer uses a phase shifter device configured to accept a noise containing frequency signal from a voltage controlled oscillator (VCO) circuit, such as an integer-N single loop PLL synthesizer, as well as noise reducing control signals from a noise detecting sensor or circuit, and output a noise reduced VCO frequency signal. In some embodiments, the noise reducing sensor may be formed from a second, lower noise, phase locked loop circuit. The frequency synthesizer circuit, noise detecting sensor, and the phase shifter device are configured to all run continuously, with the noise reducing sensor and frequency shifter continually acting to reduce noise, produced by higher noise integer-N PLL frequency synthesizer.