PLL Offset Compensation Circuit Reduces Static Phase Error
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Solution Overview
Problem
Conventional phase locked loops (PLLs) in integrated circuits suffer from variations due to device mismatch, offset, and leakage, leading to unsatisfactory static phase error compensation across process variation, voltage, and temperature (PVT), resulting in reduced production yield and increased costs.
Innovation Solution
The implementation of an offset compensation circuit with a programmable current source, which eliminates fixed path delay elements and provides adjustable offset current to the charge pump, allowing for better compensation of PVT mismatches and reduction of deterministic jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If fixed path delay elements are used to tune static phase error, then phase error compensation is achieved, but deterministic jitter and inter symbol interference are introduced
Solution Approach 1:
The patent changes the parameter being adjusted from fixed path delay (time domain) to variable current (electrical domain). The programmable current source provides adjustable current to the charge pump, which dynamically compensates for static phase error without introducing the deterministic jitter and inter symbol interference associated with fixed RC delay elements.
2Device complexity
If fixed delay setting is used in conventional PLL, then circuit simplicity is maintained, but satisfactory SPE compensation across PVT variation cannot be achieved
Solution Approach 1:
The patent introduces dynamic adjustability to the charge pump current through a programmable current source. This allows the PLL to adapt to process, voltage, and temperature variations by dynamically changing the current level, thereby maintaining satisfactory static phase error compensation across PVT conditions while managing the increased complexity through programmable control.
Solution Approach 2:
The patent implements a feedback mechanism where the PLL measures the actual static phase error and uses this information to programmably adjust the charge pump current. This closed-loop approach ensures accurate SPE compensation across PVT variations by continuously adapting the current level based on measured performance.
3Productivity
If programmable current source is used to compensate PVT mismatches, then production yield is improved, but device complexity increases
Solution Approach 1:
The patent enables the PLL to self-adjust by measuring its own static phase error and programmably modifying its charge pump current accordingly. This self-service capability allows the circuit to compensate for PVT mismatches autonomously, improving production yield without requiring external calibration equipment or complex external control systems.
Data Source
AI summary
An apparatus and a method for improving production yield of phase locked loops (PLLs) have been disclosed. One embodiment of the apparatus includes a PLL comprising a charge pump and an offset compensation circuit coupled to the charge pump to provide an offset current to the charge pump to reduce a static phase error of the PLL caused by a mismatch in at least one of a process variation, a voltage, and a temperature. Other embodiments are described and claimed.