PLL Parameter Switching for Fast Acquisition and Low Noise
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Solution Overview
Problem
Phase-locked loops (PLL) used in frequency synthesizers face challenges in optimizing their performance due to increased switching time during acquisition mode, which is not efficiently addressed by existing technologies.
Innovation Solution
A system and method that includes a mode detection circuit and a parameter-switching network to dynamically adjust the operating parameters of a phase-locked loop, allowing it to switch between modes and optimize performance by changing key circuit values such as charge pump current and resistor values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the phase-locked loop uses a feedback loop to minimize noise in track mode, then noise is reduced, but switching time in acquisition mode increases
Solution Approach 1:
The patent implements dynamic parameter switching in the phase-locked loop by detecting the operating mode (acquisition or track) and automatically adjusting circuit parameters such as charge pump current and resistor values. This allows the system to optimize performance for each mode: using parameters that enable fast acquisition when switching between frequencies, and parameters that minimize noise when locked on a frequency. The mode detection circuit triggers parameter changes that dynamically adapt the PLL behavior to current operational requirements.
2Speed
If duplicate frequency synthesizers are used to support fast switching, then switching speed is improved, but device complexity increases
Solution Approach 1:
The patent achieves fast switching performance without requiring duplicate synthesizers by changing the parameters of the existing PLL circuit based on operating mode. Specifically, the charge pump current and resistor values are adjusted according to whether the system is in acquisition or track mode. This parameter adaptation allows a single synthesizer to exhibit different behavioral characteristics optimized for each mode, eliminating the need for multiple parallel synthesizer circuits while maintaining fast switching capability.
Data Source
AI summary
A system and method of operating a phase-locked loop frequency synthesizer is disclosed herein. The disclosed method includes defining a first set of operating parameters applicable to operation of a phase-locked loop of the synthesizer in a first mode and defining a second set of operating parameters applicable to operation of the phase-locked loop in a second mode. A first detection signal is generated so as to initiate transition of the phase-locked loop into the second mode. The method further includes configuring, at least in part in response to the first detection signal, the phase-locked loop to operate in accordance with the second set of operating parameters.