PLL Performance Indicator for HP/LP Path Alignment
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Solution Overview
Problem
Digital phase-locked loops (PLLs) in polar transmitters face challenges in aligning high pass and low pass modulation paths, leading to distortion and reduced performance due to mismatched timing and amplitude of frequency modulation signals, which complicates calibration and is affected by oscillator non-linearity over time.
Innovation Solution
The implementation of performance indicator circuitry that calculates a value based on loop filter signals, independently decoupling the phase path from the amplitude path, allowing for LP/HP delay and gain compensation, thereby aligning the high pass and low pass signals and optimizing PLL performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If digital phase-locked loops are used in polar transmitters, then clock generation and alignment precision is improved, but alignment of high pass and low pass modulation paths becomes difficult leading to distortion
Solution Approach 1:
The patent introduces an intermediary calibration signal that passes through both the high pass and low pass modulation paths. This calibration signal serves as a mediator to measure and compare the timing and amplitude characteristics of both paths, enabling precise alignment without direct complex interactions between the paths themselves.
Solution Approach 2:
The patent implements a feedback mechanism where the calibration signal traverses the modulation paths and returns information about their alignment status. This feedback enables automatic adjustment of delay and gain parameters to optimize the alignment between high pass and low pass paths, resolving the complexity of manual alignment.
2Manufacturing precision
If calibration is performed to align modulation paths, then distortion is reduced, but calibration complexity and time increase
Solution Approach 1:
The patent performs calibration actions in advance by injecting a calibration signal before normal operation. The delay and gain parameters are predetermined through this preliminary calibration process, storing the optimized values for subsequent use. This eliminates the need for complex real-time calibration during operation.
Solution Approach 2:
The patent systematically varies delay and gain parameters during the calibration process to find optimal values. By changing these parameters in a controlled manner and measuring the resulting alignment quality, the system automatically determines the best configuration without requiring complex manual adjustment procedures.
3Reliability
If oscillator non-linearity is present over time, then PLL performance degrades, but compensating for it increases system complexity
Solution Approach 1:
The patent enables the PLL system to self-calibrate by using its own internal calibration signal and performance indicator circuitry. The system automatically detects degradation due to oscillator non-linearity and adjusts its parameters accordingly, without requiring external intervention or complex additional compensation hardware.
Solution Approach 2:
The patent replaces complex mechanical or hardware-based compensation mechanisms with digital signal processing techniques. The calibration signal approach and digital parameter adjustment substitute for analog compensation circuits, reducing overall system complexity while maintaining reliability.
Data Source
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AI summary
Performance indicator circuitry is provided for characterizing performance of a phase locked loop (PLL) in a phase path of a polar modulator or polar transmitter that is used to generate a phase modulated RF signal. The PLL includes an oscillator, a high pass path, and a low pass path. The low pass path includes a loop filter. The performance indicator circuitry includes first input circuitry and parameter calculation circuitry. The first input circuitry is configured to input a loop filter signal from the loop filter. The parameter calculation circuitry is configured to compute a value for a performance indicator based on the loop filter signal and control or characterize an aspect of operation of the PLL based on the value.