PLL Frequency Synthesizer PFD Architecture for Low Jitter
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Solution Overview
Problem
Existing frequency synthesis methods, such as phase locked loop (PLL) frequency synthesizers, face challenges in reducing jitter due to noise introduced by components like phase/frequency detectors (PFDs), which are not adequately addressed by previous solutions that focus on voltage-controlled oscillators (VCOs) and loop filters.
Innovation Solution
The solution involves amplifying and isolating the PFD signal in the PLL by employing multiple PFDs to form compound structures that amplify clean phase-tracking error signals and cancel common-mode noise, thereby improving signal-to-noise ratio and reducing jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single PFD is used in the PLL, then the device complexity is low, but the jitter performance deteriorates due to insufficient signal amplification and noise cancellation
Solution Approach 1:
The single PFD is segmented into multiple parallel PFDs (first PFD, second PFD, third PFD, fourth PFD) with different time shifts. Each PFD processes the phase difference independently, and their outputs are combined to achieve noise cancellation and improved jitter performance while maintaining manageable complexity through modular architecture
Solution Approach 2:
The outputs of multiple parallel PFDs are merged through a summer or adder to produce a combined error signal. This merging process achieves coherent addition of the desired phase-tracking signal while incoherent addition of uncorrelated noise components, resulting in improved signal-to-noise ratio and reduced jitter
2Measurement precision
If multiple parallel PFDs with time shifts are employed, then the jitter is reduced through noise cancellation, but the device complexity increases due to additional components
Solution Approach 1:
The multiple PFDs are configured with predetermined time shifts applied to their phase comparison operations before the signals are combined. This preliminary time-shifting action ensures that the noise components from different PFDs are uncorrelated when combined, enabling effective noise cancellation through statistical averaging while maintaining a systematic design approach
Solution Approach 2:
The invention changes the temporal parameter of the PFD operations by introducing different time shifts to each parallel PFD. This parameter modification transforms the phase comparison process across multiple time instances, enabling the system to cancel noise through temporal diversification while maintaining a relatively simple hardware architecture
Data Source
AI summary
A phase locked loop frequency synthesizer has a controlled oscillator for generating an output signal at a desired frequency, a phase/frequency detector module for comparing a feedback signal derived from the controlled oscillator with a reference signal to generate an error signal, a loop filter for processing said at least one error signal from said phase/frequency detector module to generate a combined control signal for the controlled oscillator. The gain of the phase/frequency detector module can be adjusted, preferably by varying the pulse width and pulse cycle, to maintain the overall gain of the phase locked loop within a given range and thereby maximize signal to noise ratio.