PLL Phase Frequency Detector Layout for Oscillator Spur Suppression
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Solution Overview
Problem
Conventional phase locked loops (PLLs) in cellular phones experience performance degradation due to frequency drifting of the oscillation signal from free-running oscillators, leading to spur generation that degrades communication performance.
Innovation Solution
A modified PLL design with a phase frequency detector (PFD) that selectively controls the conversion factor K to reduce spurs by matching signal paths and maximizing power supply rejection ratio (PSRR), thereby compensating for oscillator drift and reducing unwanted signal coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a free running oscillator is used to provide oscillation signal to PLL, then device complexity is reduced and ease of manufacture is improved, but frequency drift occurs leading to spur generation that degrades communication performance
Solution Approach 1:
The patent implements a feedback mechanism where the phase frequency detector continuously monitors the phase and frequency difference between the reference signal and the feedback signal, generating an error signal that is fed back to the charge pump to adjust the control voltage, thereby compensating for oscillator drift and suppressing spur generation while maintaining the simplicity of using a free running oscillator
Solution Approach 2:
The patent introduces intermediate components including a phase frequency detector, charge pump, and loop filter that act as mediators between the free running oscillator and the PLL output. These intermediaries process and condition the signals to eliminate the harmful effects of oscillator drift without requiring a more complex reference oscillator
2Device complexity
If conventional PLL design is used with free running oscillator, then device complexity is minimized, but spurious components are generated that degrade signal quality
Solution Approach 1:
The patent converts the harmful effect of oscillator drift into a beneficial feedback signal. The phase frequency detector detects the drift-induced phase and frequency differences, and the charge pump uses these detections to generate corrective voltage adjustments that actively suppress spur generation, turning the drift problem into a self-correcting system
Solution Approach 2:
The patent dynamically changes the control voltage parameter applied to the voltage controlled oscillator based on the detected phase and frequency errors. By continuously adjusting this voltage parameter in response to drift conditions, the system maintains stable operation and minimizes spurious components while keeping the overall device complexity low
Data Source
AI summary
Embodiments of this disclosure include methods in which spurs generated by the drifting of an oscillation frequency of an oscillation signal provided by a free-running oscillator may be minimized and/or eliminated from an output signal of a phase locked loop (PLL). Methods include minimizing the mixing gain between the oscillation signal and a power signal provided to the PLL. The oscillation signal and the power signal may be mixed in a phase frequency detector (PFD) included in the PLL. The minimizing of the mixing gain for the PFD also minimizes the degrading effect that the spurs have on the overall performance of the communications device. The mixing gain may be minimized by minimizing the impedance provided at nodes included in the PFD where the oscillation signal and the power signal mix. The mixing gain may also be minimized by maximizing the power supply rejection ratio for the PFD.