PLL Feedback Loop Using Phase Accumulators for Fast Fine Tuning

The patent changes the fundamental operating parameters of the PLL by using phase accumulators clocked at reference and output frequencies instead of traditional frequency dividers. This allows the system to achieve high frequency resolution through digital phase accumulation and comparison, rather than relying on large divider values that would slow down the loop response. The resolution is achieved through the precision of digital phase measurement rather than through the magnitude of division factors.

The patent replaces the traditional analog loop filter with a digital signal processing approach using phase accumulators and a digital phase comparator. This substitution allows for precise control of the loop transfer function through digital means, enabling the system to achieve low phase noise performance without requiring a narrow analog filter bandwidth. The digital processing can selectively filter noise components while maintaining fast response to frequency changes.

The patent introduces phase accumulators as intermediary elements between the frequency dividers and the phase comparator. These accumulators integrate phase information over multiple cycles, effectively mediating between the coarse frequency division and the fine phase measurement requirements. This intermediary structure enables high resolution frequency synthesis while maintaining relatively simple divider circuits, as the accumulation process enhances the measurement precision without requiring complex high-value dividers.