PLL Synchronization Using Dual-Rate Phase Alignment
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Solution Overview
Problem
Existing methods for synchronizing phase-locked loops (PLL) to both low-frequency and high-frequency reference clocks are either complex and costly or inflexible, lacking automatic phase adjustments and proper alignment in environments with wander and jitter.
Innovation Solution
A method involving independent high-speed sampling of both high-frequency and low-frequency clocks, with high-rate phase difference measurement and low-rate phase adjustment, allowing flexible alignment and periodic realignment, ensuring accurate synchronization and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the PLL bandwidth is reduced to synchronize with low-frequency clock, then synchronization accuracy with low-frequency clock is improved, but the locking time becomes unacceptably long
Solution Approach 1:
The patent divides the synchronization task into two independent PLLs: a high-frequency PLL for fast locking and a low-frequency PLL for accurate synchronization. Each PLL operates independently with its own optimized bandwidth, eliminating the trade-off between locking time and synchronization accuracy.
Solution Approach 2:
The patent introduces a dual-PLL architecture that operates in two different frequency dimensions simultaneously. The high-frequency PLL handles rapid acquisition while the low-frequency PLL ensures precise long-term synchronization, effectively resolving the time-accuracy trade-off by operating in separate temporal domains.
2Speed
If the PLL bandwidth is increased to reduce locking time, then response speed is improved, but synchronization accuracy with low-frequency clock deteriorates
Solution Approach 1:
The patent segments the response function into two parts: the high-frequency PLL provides fast response for rapid locking, while the low-frequency PLL ensures accurate long-term synchronization. This segmentation allows each PLL to be optimized for its specific function without compromise.
Solution Approach 2:
The high-frequency PLL acts as an intermediary that provides rapid initial locking, which then guides the low-frequency PLL to achieve precise synchronization. The dual-PLL system mediates between speed and accuracy requirements through coordinated operation.
3Adaptability or versatility
If a hybrid method with NCO is used to align PLL output with low-frequency sync, then synchronization flexibility is improved, but device complexity and cost increase
Solution Approach 1:
The patent extracts the low-frequency synchronization function from the high-frequency PLL and implements it as a separate dedicated low-frequency PLL. This extraction eliminates the need for complex NCO mechanisms and mode-switching logic, reducing overall system complexity while maintaining synchronization flexibility.
Solution Approach 2:
The dual-PLL architecture provides universal synchronization capability that can handle both high-frequency and low-frequency references simultaneously. Each PLL is designed to be multi-functional, capable of operating with different reference frequencies while maintaining the same basic architecture.
4Device complexity
If low-frequency sync is sampled using high-frequency reference clock, then phase measurement is simplified, but sampling flexibility and adaptability are reduced
Solution Approach 1:
The patent segments the measurement function into two independent measurement paths: one for high-frequency reference and one for low-frequency sync. Each path uses its own phase detector optimized for its frequency range, maintaining measurement simplicity while maximizing sampling flexibility.
Solution Approach 2:
The patent implements dynamic phase adjustment where the low-frequency PLL can independently adjust its phase based on its own measurements, rather than being constrained by the high-frequency sampling rate. This dynamic operation provides adaptability to various sync conditions while keeping measurement logic simple.
Data Source
AI summary
A phase-locked loop to is simultaneously synchronized to high and low frequency clocks by (i) locking an output of the phase-locked loop to a high-frequency reference clock, (ii) measuring at a high rate a first phase difference between the high-frequency reference clock and the output of the phase-locked loop, (iii) measuring at a high rate a second phase difference between a low-frequency reference clock and the output of the phase-locked loop; (iv) computing at a low rate from said first and second phase differences a third phase difference between the high-frequency and low frequency clocks; (v) combining at a low rate said third phase difference with said second phase-difference to obtain a total phase difference; and (vi) adjusting the output of the phase-locked loop at a low rate to reduce the obtained total phase difference.