Fractional-N PLL Feedback Phase Correction for Spur Reduction
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Solution Overview
Problem
Frequency synthesizer circuits in wireless communication systems face phase inconsistencies due to frequency division in feedback configurations, leading to noise and spurs in the phase locked loop (PLL) feedback path.
Innovation Solution
A frequency synthesizer circuit with phase correction circuitry that includes a comparator, loop filter, oscillator, and fractional divider, using delta sigma modulators and digital delay control circuitry to stabilize the phase difference between the reference clock and output signal, reducing delta-sigma noise and spurs by up to 10×.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If frequency division is used in feedback configuration of frequency synthesizer, then frequency synthesis capability is achieved, but phase inconsistencies and noise are introduced in the PLL feedback path
Solution Approach 1:
A phase correction circuit is introduced as an intermediary component in the feedback path between the fractional divider and the phase detector. This circuit includes delay elements and selection logic that actively compensate for phase errors introduced by frequency division, thereby mediating between the frequency synthesis function and phase stability requirements
Solution Approach 2:
The patent implements a feedback mechanism where the phase correction circuit continuously monitors and adjusts the phase of the feedback signal based on the phase detector output. The correction amount is dynamically adjusted to maintain stable phase relationship despite the phase-inverting effect of frequency division
2Object-generated harmful factors
If phase correction circuitry is added to stabilize phase error, then noise and spurs are reduced, but device complexity increases
Solution Approach 1:
The phase correction circuit is segmented into modular functional blocks: delay elements, selection logic, and control circuitry. This segmentation allows independent optimization of each block and simplifies the overall design and implementation while achieving effective phase correction
Solution Approach 2:
The circuit dynamically changes the delay parameter of the feedback signal based on the detected phase error. By adjusting the delay amount through the selection logic and control circuitry, the system achieves phase stabilization without requiring complex active correction mechanisms
Data Source
AI summary
A frequency synthesizer circuit is disclosed. The frequency synthesizer circuit includes a comparator circuit coupled to a reference clock and a phase-corrected output signal. The frequency synthesizer circuit also includes a loop filter coupled to the comparator circuit. The frequency synthesizer circuit also includes an oscillator coupled to the loop filter. The frequency synthesizer circuit also includes a fractional divider coupled to an output of the oscillator. The frequency synthesizer circuit also includes phase correction circuitry that corrects a phase of an output of the fractional divider to produce the phase-corrected output signal.