High-Gain PLL Phase Detector Architecture for Low Offset Phase Noise
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Solution Overview
Problem
High gain phase detector techniques for phase-locked loops (PLLs) are sensitive to process and temperature variations, supply noise, and limited supply voltage, which degrades PLL jitter performance and phase noise at low frequency offsets.
Innovation Solution
A fully differential loop filter structure with high gain phase detectors of opposite polarity for supply rejection, combined with a delta-sigma modulator to reduce quantization noise, and a digital-to-time converter to minimize noise folding, while leveraging charge pump techniques to increase effective supply voltage and reduce sensitivity to supply noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high gain phase detector techniques are used to achieve low phase noise at low frequency offsets, then phase noise performance is improved, but sensitivity to process and temperature variations increases
Solution Approach 1:
The patent employs dual-gain phase detector structures where one path provides high gain for low phase noise while the other path provides PT-insensitive gain. The system dynamically selects or combines these paths based on operating conditions, changing the effective gain parameter to optimize both phase noise performance and reliability across different processes and temperatures.
Solution Approach 2:
The patent creates a composite phase detector system that combines multiple detector types (slope-based sampling PD and Up/Down RC charging circuits) into a unified structure. This composite structure leverages the strengths of each detector type while compensating for their individual weaknesses, achieving both high gain and PT insensitivity simultaneously.
2Power
If slope-based sampling PD structure is used to achieve high gain, then gain is improved, but sensitivity to supply noise increases
Solution Approach 1:
The patent segments the phase detector function into multiple independent paths: one slope-based sampling PD path for high gain and one Up/Down RC charging circuit path for supply noise immunity. By dividing the detection function across these segments, the system can select the appropriate path based on supply noise conditions while maintaining high overall gain.
3Reliability
If Up/Down RC charging circuits are used to achieve PT-insensitive gain, then robustness against PT variation is improved, but limitation by supply voltage increases
Solution Approach 1:
The patent merges the Up/Down RC charging circuits with charge pump techniques, combining the PT-insensitive gain characteristic of the RC circuits with the supply voltage boosting capability of the charge pump. This integration allows the system to overcome supply voltage limitations while maintaining robustness against PT variations.
4Measurement precision
If high gain phase detectors are used to reduce detector noise, then low frequency phase noise is improved, but device complexity increases
Solution Approach 1:
The patent implements a dynamic phase detector system that can switch between different detection paths (high gain slope-based path and PT-insensitive RC path) based on real-time operating conditions. This dynamic adaptation allows the system to achieve low detector noise when needed while avoiding unnecessary complexity in stable operating conditions, optimizing the trade-off between performance and complexity.
Data Source
AI summary
In described examples, an apparatus comprises a multi-modulus divider (MMD) having a divider input, a divisor input, and a divider output. The apparatus also comprises a phase detector (PD) having a first clock input, a second clock input, and a PD output, the second clock input coupled to the divider output. The apparatus also comprises a phase to digital converter (P2DC) having a P2DC input and a P2DC output, the P2DC input coupled to the PD output. The apparatus further comprises a delta-sigma modulator having a third clock input, a modulator input, and a modulator output, the third clock input coupled to the divider output, the modulator input coupled to the P2DC output, and the modulator output coupled to the divisor input.