PLL Phase Error Correction Using Divider-Based Digital Calibration
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Solution Overview
Problem
Phase-locked loops (PLLs) in wireless and digital applications experience prolonged locking times due to reliance on voltage-controlled oscillators for phase error calibration, which degrades performance and fails to meet certain application requirements.
Innovation Solution
The method involves phase error correction in two steps, calculating and compensating for phase errors at frequency dividers instead of relying on voltage-controlled oscillators, with adjustments made in four clock cycles using a feedback divider's gain modification based on calculated values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional PLL locking methods are used with large loop bandwidth during locking stage, then locking time is reduced, but performance is degraded due to dependence on VCO frequency change for phase error calibration
Solution Approach 1:
The patent replaces the voltage-controlled oscillator (VCO) based phase error calibration mechanism with a digitally controlled oscillator (DCO) and time-to-digital converter (TDC) based digital calibration system. This substitution allows phase error calibration to be performed through digital time measurement and calculation rather than relying on analog VCO frequency changes, thereby resolving the contradiction between fast locking and accurate calibration.
Solution Approach 2:
The patent introduces a time-to-digital converter (TDC) as an intermediary component that measures the time difference between reference clock edge and target clock edge. This intermediary enables accurate phase error measurement through time domain sampling, allowing the system to achieve both fast locking and precise calibration without directly relying on VCO frequency modulation.
2Speed
If PLL locking is performed with excessive large loop bandwidth, then locking speed is improved, but phase error calibration accuracy deteriorates
Solution Approach 1:
The patent transitions from frequency domain phase error calibration (traditional VCO-based method) to time domain phase error measurement (TDC-based method). By measuring time differences between clock edges and converting to phase error through digital calculation, the system achieves high precision phase measurement independent of loop bandwidth settings, thus resolving the contradiction between locking speed and measurement precision.
Solution Approach 2:
The patent performs preliminary time difference measurement during the locking process itself, rather than requiring separate calibration phases. The TDC continuously measures time offsets between reference and target clocks, and the controller uses these measurements to dynamically adjust the DCO, enabling phase error calibration to occur concurrently with locking operations.
Data Source
AI summary
Systems and methods for performing phase error correction are provided. A reference clock signal and a target clock signal are received. A first value is generated based on a first amount of time between a first edge of the reference clock signal and a corresponding first edge of the target clock signal. A phase of the target clock signal is adjusted a first time based on a given amount computed using the first value. After the phase of the target clock signal is adjusted, a second value is generated based on a second amount of time between a second edge of the reference clock signal and a corresponding second edge of the target clock signal. The phase of the target clock signal is adjusted a second time based on the given amount, the first value, and the second value.