Multi-PLL Phase Alignment with Background Drift Compensation

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Solution Overview

Problem

In wireless communication devices, particularly in 5G systems using millimeter waves, maintaining accurate phase alignment between multiple Phase Locked Loops (PLLs) is challenging due to stringent phase noise requirements and temperature drift, which complicates beamforming and increases noise contributions, making frequent recalibration necessary and resource-intensive.

Innovation Solution

A system and method for phase alignment of multiple PLLs, where each PLL generates a feedback signal that is compared by phase detectors to generate adjustment signals, allowing for slow closed-loop calibration to minimize accumulation errors and compensate for temperature drift, enabling calibration without interrupting ongoing transmission and reducing the need for frequent antenna recalibration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate PLLs are used for each transceiver to reduce noise correlation and improve SNR, then signal-to-noise ratio improves, but phase alignment between PLLs becomes difficult to maintain

Engineering Contradiction:
Improvesignal-to-noise ratioVSAvoidphase alignment
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The patent implements a feedback mechanism where phase detectors continuously monitor the phase relationship between feedback signals from multiple PLLs and generate adjustment signals. These adjustment signals are fed back to the PLLs to correct phase deviations, ensuring phase alignment is maintained while allowing separate PLL operation for noise reduction.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent introduces phase detectors and adjustment signal generation as intermediary components between the separate PLLs. These intermediaries measure phase differences and generate corrective signals, enabling phase alignment without requiring direct coupling or synchronization between the independent PLLs.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If frequent recalibration is performed to compensate for temperature drift and maintain phase alignment, then phase alignment accuracy improves, but system complexity and resource consumption increase

Engineering Contradiction:
Improvephase alignment accuracyVSAvoidcalibration system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent enables the PLL system to perform self-calibration through automatic feedback mechanisms. The phase detectors continuously monitor phase alignment and the adjustment signals automatically correct deviations, eliminating the need for external manual calibration and reducing system complexity.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent implements continuous phase monitoring and adjustment rather than periodic recalibration. The feedback loop operates continuously to maintain phase alignment, ensuring constant accuracy without the resource-intensive interruptions of frequent manual recalibration.

Inventive Principle:
Principle #20Continuity of useful action

3Measurement precision

If calibration algorithms are run to compensate for temperature drift, then phase alignment is maintained, but transmission and reception are interrupted

Engineering Contradiction:
Improvephase alignmentVSAvoidcommunication continuity
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent implements continuous background calibration that operates simultaneously with normal transmission and reception. The phase detectors and adjustment mechanisms work continuously without interrupting communication operations, maintaining both phase alignment accuracy and communication productivity.

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The patent performs preliminary phase alignment adjustments continuously in the background before deviations affect communication performance. This proactive approach maintains phase alignment without requiring interruptive recalibration operations.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces accumulation errors, allows for infrequent calibration based on temperature drift, and maintains accurate phase alignment between PLLs, improving signal-to-noise ratio and reducing power consumption by enabling background calibration without affecting ongoing operations.

Implementation Method 1

a phase comparator arrangement configured to output a respective control signal to control the oscillator in response to a detection of a phase deviation between a reference signal and the feedback signal

Methodology Applied
Scientific EffectPhase detection:

Implementation Method 2

a frequency divider configured to generate a feedback signal by dividing the respective output signal

Methodology Applied
Scientific EffectFrequency division:

Data Source

PatentEP3476049B1Method and system for phase alignment of multiple phased locked loops
Publication Date: 2020.01.29 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
  • EP3476049B1 patent drawingFigure 1a~1b
  • EP3476049B1 patent drawingFigure 2~3
  • EP3476049B1 patent drawingFigure 4

AI summary

A system and method for phase alignment of multiple PLLs are disclosed. The system comprises a plurality N of PLLs (PLL_1...PLL_N) and a plurality N of phase detectors (DET_1...DET_N). The plurality N of phase detectors and the plurality N of PLLs are connected in a loop such that an i-th phase detector (DET_i) is configured to receive an i-th feedback signal (FB_i) generated from the i-th PLL and an (i+1 )-th feedback signal (FB_i+1) generated from the (i+1)-th PLL, and the N-th phase detector (DET_N) is configured to receive the first feedback signal (FB_1) generated from the first PLL and the N-th feedback signal (FB_N) generated from the N-th PLL. The an i-th phase detector (DET_i) is configured to generate an i-th adjustment signal indicating an i-th phase difference between the i-th and (i+1)-th feedback signals for adjusting a phase of the i-th or (i+1)-th PLL, wherein i=1, 2, 3,...N-1. The N-th phase detector (DET_N) is configured to generate a N-th adjustment signal indicating a N-th phase difference between the first and N-th feedback signals.