Sigma-Delta Time-to-Digital Conversion for Precise PLL Phase Error
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Solution Overview
Problem
Conventional digital phase-locked loops (PLLs) face limitations such as low accuracy, large area requirements, and high power consumption, making them unsuitable for high-precision time-to-digital conversion applications.
Innovation Solution
A sigma-delta based PLL architecture that incorporates a sigma-delta modulator and a digital loop filter to convert phase information into the digital domain, utilizing oversampling and noise-shaping techniques to minimize quantization noise and achieve low jitter and high resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional digital PLL architecture is used, then the system can generate output signal based on input reference signal, but the measurement precision of time-to-digital conversion is low
Solution Approach 1:
The patent replaces conventional digital PLL components with a sigma-delta modulator-based time-to-digital converter that uses oversampling and noise-shaping techniques. This substitution transforms the phase detection mechanism from traditional digital counting to sigma-delta modulation, achieving higher measurement precision by converting analog phase differences into high-resolution digital values through multiple oversampled measurements and digital filtering
Solution Approach 2:
The patent changes the operating parameters of the PLL by implementing a sigma-delta modulator that operates at a higher sampling frequency than the reference signal frequency. This parameter change enables oversampling, which increases the effective resolution of time-to-digital conversion by distributing quantization noise across a wider frequency range and allowing digital filtering to recover fine phase differences
2Area of stationary object
If conventional digital PLL is implemented, then the system can perform phase comparison, but the area requirement is large
Solution Approach 1:
The patent extracts the time-to-digital conversion function from the traditional PLL phase detector and implements it separately using a sigma-delta modulator. This extraction allows the main PLL loop to remain simple while the high-precision measurement function is performed by the dedicated sigma-delta TDC module, reducing the overall area requirement compared to implementing high precision throughout the entire conventional PLL
Solution Approach 2:
The patent uses a sigma-delta modulator that creates multiple copies of the phase error signal through oversampling. By taking multiple measurements of the same phase difference at different time instances and processing them through digital filtering, the system achieves high measurement precision without requiring large analog circuitry, thus reducing area while maintaining accuracy
3Use of energy by stationary object
If conventional digital PLL is used, then the system can lock to reference frequency, but the power consumption is high
Solution Approach 1:
The patent replaces the conventional analog phase detector and charge pump with a digital sigma-delta modulator-based TDC. This substitution eliminates power-hungry analog components while maintaining the essential PLL function of phase comparison and frequency locking, thereby reducing power consumption without compromising stability
Solution Approach 2:
The sigma-delta modulator uses periodic oversampling of the phase error signal at a frequency higher than the reference signal frequency. This periodic action allows the system to accumulate phase error information over multiple cycles and process it through digital filtering, achieving stable frequency locking with lower instantaneous power consumption compared to continuous high-speed analog operation
4Measurement precision
If sigma-delta modulator with oversampling is used, then the measurement precision is improved, but the device complexity increases
Solution Approach 1:
The patent introduces a decimation filter as an intermediary component between the sigma-delta modulator and the PLL loop filter. This intermediary processes the high-rate oversampled output from the modulator and converts it to a lower rate signal suitable for the PLL, simplifying the overall architecture by providing a clear separation between the high-resolution measurement stage and the frequency control stage
Data Source
AI summary
Systems, methods, and circuits provide a time to digital converter comprising a sigma-delta modulator. The sigma-delta based time to digital converter may receive an analog signal representing a phase error between a reference clock signal and a feedback clock signal and generate a digital signal representing the phase error. The sigma-delta modulator may comprise a subtractor, an integrator, a feedback path, and a quantizer. The subtractor may receive the analog signal and subtract a feedback signal from the analog signal and the integrator may integrate the output of the subtractor. The sigma-delta modulator may accumulate a voltage or a charge over a capacitor as pulses are received from the analog signal and after a number of clock cycles, the capacitor may be discharged to generate a pulse in an output signal.