On-Chip PLL Phase Error Detection for Short-Term Jitter
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Solution Overview
Problem
Measuring jitter performance in phase-locked loop (PLL) circuits is challenging due to timing uncertainty in clock generation, especially with modern technology, and existing methods are either unreliable for short-term measurements or require complex hardware.
Innovation Solution
An all-digital instantaneous phase error detector (IPED) is used to measure peak phase error amplitude at each reference clock cycle with programmable error-detection thresholds, simplifying hardware complexity by not requiring a voltage-controlled oscillator frequency and using simple lumped delay lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large number of delay lines are deployed to detect timing uncertainty in zero-time crossing, then measurement precision is improved, but device complexity increases and additional jitter is generated
Solution Approach 1:
The patent extracts only the essential information needed for jitter measurement by using an all-digital instantaneous phase error detector that measures peak phase error amplitude. Instead of deploying a large number of delay lines to detect zero-time crossing metastability, the invention extracts phase error signals from the PFD output and processes them digitally, thereby reducing hardware complexity while maintaining measurement precision.
Solution Approach 2:
The patent replaces the mechanical/analog approach of using multiple delay lines and detecting metastability in zero-time crossing with an all-digital phase error detection system. The instantaneous phase error detector uses digital logic to measure peak phase error amplitude, substituting complex analog timing detection with simpler digital signal processing.
2Measurement precision
If analog charge pump is used for jitter measurement, then measurement capability is improved, but manufacturing precision requirements increase due to transistor mismatch
Solution Approach 1:
The patent substitutes the analog charge pump system with an all-digital instantaneous phase error detector. By using digital logic circuits instead of analog transistors and charge pumps, the invention eliminates the need for high manufacturing precision and transistor matching, while maintaining the ability to measure jitter accurately through digital phase error detection.
3Productivity
If instantaneous jitter measurement is performed, then productivity is improved, but reliability decreases due to sensitivity to on-chip variations
Solution Approach 1:
The patent implements a feedback mechanism where the instantaneous phase error detector continuously monitors phase error signals and the system uses this information to maintain reliable measurements. The digital processing of phase error signals allows the system to compensate for on-chip variations through algorithmic processing, maintaining both speed and reliability.
Solution Approach 2:
The patent changes the measurement parameter from detecting metastability in zero-time crossing to measuring peak phase error amplitude. This parameter change allows instantaneous measurement while being more robust to on-chip variations, as the peak amplitude measurement is less sensitive to timing jitter and process variations than metastability detection.
Data Source
AI summary
An apparatus includes a phase-locked loop (PLL) circuit including a phase-frequency detector configured to output phase error signals. A phase error monitor circuit is configured to determine instantaneous peak phase error by logically combining the phase error signals and comparing pulse widths of the logically combined phase error signals to a programmable delay time at each reference clock cycle to determine instantaneous phase error change. A storage element is configured to store the instantaneous phase error change.