PLL Phase Error Monitoring for On-Chip Jitter Measurement
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Solution Overview
Problem
Measuring jitter performance in phase-locked loop (PLL) circuits is challenging due to increased timing uncertainty in clock generation with modern technology, and existing methods often require complex hardware and are prone to jitter degradation from on-chip variations.
Innovation Solution
An all-digital instantaneous phase error detector (IPED) is used to measure peak phase error amplitude at each reference clock cycle with programmable error-detection thresholds, reducing hardware complexity by detecting phase error amplitude at the phase-frequency detector output, and employing simple lumped delay lines to simplify jitter measurement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large set of latches and delay lines are deployed to detect timing metastability, then jitter measurement capability is improved, but additional jitter is generated and hardware complexity increases
Solution Approach 1:
The patent extracts only the essential phase error detection function from the complex latch-based metastability detection system. By using a simple phase-frequency detector to generate phase error signals and a minimal delay line for threshold comparison, the invention achieves jitter measurement without the harmful side effects of large latch arrays and extensive delay line networks.
Solution Approach 2:
The invention replaces expensive, complex metastability detection hardware with simple, low-cost digital logic elements. The phase-frequency detector and single delay line constitute a minimal hardware footprint that consumes less power and generates less jitter compared to traditional large-scale latch-based systems.
2Measurement precision
If an analog charge pump is used for jitter measurement, then measurement functionality is achieved, but mismatch requirements of transistors increase hardware complexity
Solution Approach 1:
The patent substitutes the analog charge pump mechanism with a fully digital phase-frequency detector and logic-based phase error monitoring system. This replacement eliminates the need for precise transistor matching requirements inherent in analog circuits, while maintaining the ability to measure phase errors and determine jitter.
3Measurement precision
If conventional off-chip test nodes are used for system diagnostics, then measurement capability is provided, but measurement speed is slow and learning rate is limited
Solution Approach 1:
The patent nests the phase error monitor circuit directly within the PLL structure, embedding diagnostic functionality inside the operational circuit rather than requiring external measurement interfaces. This integration enables real-time monitoring of phase errors and jitter characteristics at the source, dramatically improving measurement speed and providing immediate feedback for yield learning.
Data Source
AI summary
An apparatus includes a phase-locked loop (PLL) circuit including a phase-frequency detector configured to output phase error signals. A phase error monitor circuit is configured to determine instantaneous peak phase error by logically combining the phase error signals and comparing pulse widths of the logically combined phase error signals to a programmable delay time at each reference clock cycle to determine instantaneous phase error change. A storage element is configured to store the instantaneous phase error change.