PLL Phase-Error Spreading Circuit for Lower Clock Jitter
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Solution Overview
Problem
Traditional phase-locked loop (PLL) systems face challenges in tightly controlling jitter due to delayed phase correction, which is only made at the positive edge of the reference clock, resulting in phase jitter.
Innovation Solution
A phase-error spreading circuit is introduced to generate phase-spread pulses based on the relationship between time attributes of the up or down signals and phase-spread pulses, which are used to improve the responsiveness of the charge pump and voltage-controlled oscillator, allowing for more precise phase error correction and reduced jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phase error correction is made only at the positive edge of the reference clock, then the PLL system operates with simple timing control, but phase jitter increases due to delayed correction
Solution Approach 1:
The phase error correction is segmented into multiple correction opportunities throughout the reference clock cycle. Instead of a single correction at the positive edge, the phase-error spreading circuit distributes corrections across multiple time points (rising and falling edges), allowing incremental phase adjustment without waiting for the next cycle.
Solution Approach 2:
The phase error is detected and prepared for correction in advance throughout the entire reference clock cycle, not just at the positive edge. The phase-error spreading circuit continuously monitors and spreads the correction action across multiple edges, performing preliminary corrections before the traditional single correction point would occur.
2Reliability
If phase error correction is delayed until the next reference clock cycle, then the control logic remains simple, but phase jitter increases due to slower response
Solution Approach 1:
The phase correction is applied periodically at both the rising and falling edges of the reference clock signal. This dual-edge periodic action doubles the correction frequency compared to single-edge correction, improving response speed while maintaining the rhythmic, predictable nature of PLL operation.
Solution Approach 2:
The phase error correction becomes a continuous process throughout the reference clock cycle rather than a discrete event at the positive edge. The phase-error spreading circuit ensures that correction action is continuously applied at every opportunity (both edges), eliminating idle periods where no correction occurs.
Data Source
AI summary
A phase-locked loop (PLL) system including a phase-frequency detector for generating an up signal or a down signal based on a phase difference between a reference clock and a feedback clock is provided. The PLL system further includes a phase-error spreading circuit for generating phase-spread pulses based on a relationship between a first time attribute of the up signal or the down signal and a second time attribute of the phase-spread pulses. The PLL system further includes a voltage-controlled oscillator (VCO) for generating a VCO clock based on the phase-spread pulses. The PLL system may also include a charge pump that generates a pumping signal based on the phase-spread pulses.