On-Chip PLL Phase Error Detection Using Programmable Delay Thresholds
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Solution Overview
Problem
Measuring jitter performance in phase-locked loop (PLL) circuits is challenging due to timing uncertainty in clock generation, especially with modern technologies, and existing methods are either unreliable or require complex hardware, limiting on-chip diagnostics and testability.
Innovation Solution
An all-digital instantaneous phase error detector (IPED) is used to measure peak phase error amplitude at each reference clock cycle with programmable error-detection thresholds, simplifying hardware complexity by not requiring a voltage-controlled oscillator frequency and using simple lumped delay lines, and storing phase error changes for post-processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large number of delay lines are deployed to detect timing uncertainty in zero-time crossing, then timing measurement capability is improved, but additional jitter is generated that degrades measurement performance
Solution Approach 1:
The patent extracts only the necessary phase error information from the PLL output without requiring large numbers of delay lines. By using a phase error detector that outputs phase error signals and a monitor circuit that measures peak phase error amplitude, the system achieves timing measurement capability without deploying excessive delay lines that would generate additional jitter.
Solution Approach 2:
The patent introduces a phase error detector and monitor circuit as intermediary components between the PLL output and the measurement system. These intermediaries convert the complex timing uncertainty problem into measurable phase error signals, enabling accurate timing measurement without directly using large numbers of delay lines that would degrade performance.
2Device complexity
If an all-digital instantaneous phase error detector is used to simplify hardware complexity, then device complexity is reduced, but measurement precision of phase error may be compromised
Solution Approach 1:
The patent replaces complex analog measurement systems with an all-digital instantaneous phase error detector. By using digital logic circuits to detect and measure peak phase error amplitude, the system simplifies hardware complexity while maintaining measurement precision through digital signal processing and programmable error-detection thresholds.
Solution Approach 2:
The patent uses programmable error-detection thresholds that can be adjusted to optimize measurement precision for different operating conditions. By changing the threshold parameters in the digital monitor circuit, the system maintains high measurement accuracy while keeping the hardware structure simple and flexible.
3Difficulty of detecting and measuring
If off-chip test nodes are used for system diagnostics, then measurement capability is provided, but the diagnostic path is slow and learning rate for yield is limited
Solution Approach 1:
The patent moves the measurement capability from the external off-chip dimension to the internal on-chip dimension. By integrating the phase error detector and monitor circuit directly into the PLL chip, the system enables fast on-chip diagnostics without the time delays associated with external measurement paths, while also providing internal visibility of analog/digital waveforms for improved yield learning.
Data Source
AI summary
An apparatus includes a phase-locked loop (PLL) circuit including a phase-frequency detector configured to output phase error signals. A phase error monitor circuit is configured to determine instantaneous peak phase error by logically combining the phase error signals and comparing pulse widths of the logically combined phase error signals to a programmable delay time at each reference clock cycle to determine instantaneous phase error change. A storage element is configured to store the instantaneous phase error change.