PLL Phase Adjustment for Oscillator Failover Clock Switching
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Solution Overview
Problem
Switching between mismatched phase oscillator signals in clock failover configurations can lead to loss of phase lock and performance issues in electronic devices.
Innovation Solution
A clocking logic system that includes a primary and backup oscillator, a multiplexer, clock detect logic, control logic, and a phase-locked loop (PLL) with phase sample and hold logic, which adjusts the phase of the output clock signal to maintain consistency by subtracting a captured phase offset, mitigating phase shifts during failover.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple oscillator signals are used in a failover configuration, then reliability is improved, but phase consistency deteriorates
Solution Approach 1:
A phase-locked loop (PLL) is introduced as an intermediary device between the oscillators and the clock distribution network. The PLL captures the phase of the incoming oscillator signal and generates an output clock signal with consistent phase characteristics, thereby mediating the phase inconsistency problem when switching between oscillators
Solution Approach 2:
The system dynamically adjusts the phase parameter of the output clock signal by controlling the PLL's phase detector and voltage-controlled oscillator (VCO). When an oscillator failover occurs, the PLL detects the phase difference and adjusts the VCO output phase to match the new reference, maintaining phase consistency across failures
2Stability of the object's composition
If phase adjustment is implemented using PLL, then phase consistency is improved, but device complexity increases
Solution Approach 1:
The phase-locked loop is designed to serve multiple functions: it acts as a frequency synthesizer, a phase adjuster, and a signal cleaner. By making the PLL multi-functional, the patent reduces the need for separate dedicated circuits for each function, thereby limiting the increase in device complexity while achieving phase consistency
3Adaptability or versatility
If oscillators are switched during operation, then adaptability is improved, but phase lock stability deteriorates
Solution Approach 1:
The system performs preliminary phase capture and adjustment before the oscillator switch takes full effect. The PLL continuously monitors the incoming signal phase and pre-adjusts the output phase, so when the failover occurs, the phase lock is already established or quickly re-established, minimizing disruption to phase lock stability
Data Source
AI summary
Phase-locked loop (PLL) logic comprises an oscillator that produces a first oscillator signal and phase detect logic that determines a phase difference between the first oscillator signal and a second oscillator signal. After the second oscillator signal is replaced by a third oscillator signal, the phase detect logic determines another phase difference between the first oscillator signal and the third oscillator signal. The PLL removes the phase difference from the another phase difference to produce an intermediate signal. The oscillator adjusts the first oscillator signal using the intermediate signal.