Low-Bandwidth PLL Phase Demodulation With Fast Phase Detection
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Solution Overview
Problem
High-speed phase demodulation in wireless receivers is limited by the complexity and power consumption of high bandwidth phase-lock loops (PLLs), which are required to maintain lock at high data rates above 100 Megabits per second.
Innovation Solution
A low bandwidth phase-lock loop (PLL) combined with a fast phase change detection circuit, which generates multiple phases corresponding to the carrier wave and uses a fast path phase change detection scheme to maintain lock without the need for high bandwidth PLLs, allowing for high-speed demodulation at reduced complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high bandwidth phase-lock loop is used to maintain lock at high data rates, then the phase demodulation speed is improved, but the device complexity and power consumption increase
Solution Approach 1:
The patent divides the phase demodulation function into two separate components: a low bandwidth phase-lock loop for maintaining phase lock and a fast phase change detection circuit for detecting phase transitions. This segmentation allows each component to be optimized independently, achieving high-speed demodulation without requiring a high-bandwidth PLL
Solution Approach 2:
The fast phase change detection circuit acts as an intermediary that detects phase transitions and generates control signals to switch between different PLL output phases. This intermediary component enables the system to respond to high-speed phase changes without requiring the main PLL to have high bandwidth
2Speed
If a high bandwidth phase-lock loop is used to maintain lock at high data rates, then the phase demodulation speed is improved, but the power consumption increases
Solution Approach 1:
By segmenting the phase demodulation function into a low-power PLL and a fast detection circuit, the patent eliminates the need for a high-power high-bandwidth PLL, thereby reducing overall power consumption while maintaining high-speed performance
Solution Approach 2:
The patent changes the operational parameters of the PLL by using a low bandwidth configuration combined with a separate fast detection mechanism, allowing the system to achieve high-speed demodulation without the power consumption penalty associated with high-bandwidth PLL operation
3Device complexity
If a low bandwidth phase-lock loop is used, then the device complexity and power consumption are reduced, but the ability to maintain lock at high data rates deteriorates
Solution Approach 1:
The fast phase change detection circuit serves as an intermediary that compensates for the low bandwidth PLL's inability to track high-speed phase changes. It detects phase transitions and dynamically switches the feedback phase to match the incoming signal, thereby maintaining reliable phase lock despite the PLL's low bandwidth
Solution Approach 2:
The system performs preliminary phase detection using the fast detection circuit before the PLL needs to respond. By detecting phase changes in advance and preparing the appropriate feedback phase, the system ensures continuous reliable lock maintenance without requiring the PLL to respond rapidly to every phase transition
Data Source
AI summary
Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase.