PLL Clock Phase Calibration Using Delay Lines and Glitch Detection
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Solution Overview
Problem
High-speed IOs operating at lower supply voltages, such as 0.7 V or below, face challenges in energy efficiency and phase mismatches due to silicon process device mismatch and temperature variations, leading to increased jitter and reduced data margin in ultra-high-speed Ethernet SERDES.
Innovation Solution
A calibrated phase locked loop (PLL) with a digital phase spacing detector (DPSD) and programmable delay lines is used to align clock phases, employing replica cells and glitch detection to adjust VCO delay settings, ensuring accurate phase alignment and reducing systematic offsets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If high-speed IOs operate at lower supply voltage (0.7V or below) to improve energy efficiency, then energy consumption is reduced, but phase mismatches and jitter increase due to silicon process device mismatch
Solution Approach 1:
The patent applies preliminary action by performing phase calibration before normal data transmission. The calibration process uses a calibration mode to pre-adjust the clock phases from the VCO, storing the calibrated phase offsets in calibration registers. This preliminary calibration ensures that when the system switches to normal transmission mode, the phases are already aligned, preventing phase mismatches and jitter even at lower supply voltages where such mismatches would otherwise be more severe.
Solution Approach 2:
The patent implements feedback through a phase detection mechanism that monitors the actual phase differences between clock phases during calibration. The phase detector compares the calibrated phases and generates feedback signals that are used to adjust the VCO control registers, iteratively refining the phase alignment. This feedback loop continues until the phase mismatches are minimized, ensuring reliable operation at lower voltages where process variations would otherwise cause significant phase errors.
2Use of energy by moving object
If multi-clock phases are generated using a VCO to enable parallel IO scheme at lower voltage, then energy efficiency is improved, but additional random mismatches and phase errors occur
Solution Approach 1:
The patent applies segmentation by dividing the phase calibration process into separate, independent calibration operations for each clock phase. The system calibrates each phase from the VCO individually against a reference, storing each phase's calibration data in separate calibration registers. This segmented approach allows precise adjustment of each phase independently, compensating for the random mismatches introduced by silicon process variations that become more significant at lower operating voltages.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the control parameters of the VCO during calibration. The system modifies the VCO control register values to change the phase output parameters, optimizing them for minimal phase mismatch. This parameter adjustment compensates for process variations and ensures accurate phase alignment even when operating at lower supply voltages where the VCO is more sensitive to process mismatches.
3Device complexity
If clock phases are not calibrated, then device complexity is reduced, but jitter increases and data margin is reduced
Solution Approach 1:
The patent applies self-service by implementing an automatic calibration system that performs phase alignment without requiring external manual intervention. The calibration controller automatically initiates the calibration sequence, controls the phase detection process, and adjusts the VCO parameters based on the detected phase differences. This self-calibrating mechanism ensures optimal phase alignment and maximum data margin while keeping the user interface simple, effectively masking the underlying complexity of the calibration system.
Data Source
AI summary
A digital phase spacing detector with programmable delay lines is described. Each programmable delay line receives a clock. The output of the programmable delay lines is compared by a logic and then passed through a glitch detector. Each of the clocks pass through the programmable delay lines that are tuned to a point where the clock edges at the output of the delay lines are aligned and glitches start appearing at the output of the logic. A calibration scheme uses replica cells (replica of VCO cells) in the measurement path. The calibration scheme calculates the average of clock phase differences through a digital control replica buffer, and this average clock phase difference is applied to the VCO delay stage cells. The PLL is then allowed to relock with the calibrated VCO delay stage cells. This process can be repeated several times to reduce the phase errors between the clock phases.