PLL Frequency Synthesizer With Phase Interpolation for Low Jitter
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Solution Overview
Problem
Existing communication systems face challenges in synthesizing high-frequency signals with low jitter, particularly with fractional-N synthesizers, which require hardware and software elements to operate at higher speeds, straining receiver resources and introducing phase noise and spurs.
Innovation Solution
A low jitter phase-lock loop (PLL) based frequency synthesizer is developed, utilizing a first frequency divider, phase frequency detector, charge pump, low-pass filter, voltage control oscillator, phase interpolator, and CML-to-CMOS converter to achieve 1 part per billion frequency resolution with ultra-low power and area digital core, reducing phase interpolation integral non-linearity and Delta-Sigma modulator noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If fractional-N synthesizer is used to synthesize high frequency signals, then frequency resolution is improved, but hardware and software processing resources are strained and phase noise increases
Solution Approach 1:
The patent segments the frequency synthesis process into multiple stages: integer frequency synthesis stage and fractional frequency synthesis stage. The integer-N synthesizer handles the base frequency generation with high stability, while the fractional-N synthesizer adds fine frequency resolution through phase interpolation. This segmentation allows the system to achieve high frequency resolution without overloading the processing resources, as each stage operates independently with optimized resource requirements.
Solution Approach 2:
The patent introduces a phase interpolator as an intermediary component between the integer-N and fractional-N synthesis paths. The phase interpolator takes the output from the integer-N synthesizer and applies fractional phase shifts to generate the final high-resolution frequency signal. This intermediary approach allows the system to achieve fine frequency control without requiring the entire signal processing chain to operate at the high speeds needed for pure fractional-N synthesis, thereby reducing processing resource strain.
2Measurement precision
If fractional-N synthesizer operates at higher speeds, then frequency resolution is improved, but phase noise and spurs increase
Solution Approach 1:
The patent separates the frequency synthesis into integer and fractional components, where the integer-N part operates at lower speeds with high stability, generating minimal phase noise. The fractional part operates at higher speeds but only for the phase interpolation function, which has a smaller impact on overall phase noise. This segmentation allows the system to achieve high frequency resolution while minimizing the generation of phase noise and spurs.
Solution Approach 2:
The patent employs feedback mechanisms in both the integer-N and fractional-N synthesizer paths to maintain signal stability and reduce phase noise. The phase-locked loop (PLL) feedback ensures that the VCO output remains synchronized with the reference frequency, while additional feedback paths in the fractional-N section help suppress spurs and phase noise generated during high-speed fractional frequency synthesis.
3Device complexity
If integer-N synthesizer is used, then design is simple and spurs are reduced, but frequency resolution is limited
Solution Approach 1:
The patent merges the integer-N synthesizer and fractional-N synthesizer into a hybrid architecture. The integer-N synthesizer provides the stable, simple base frequency generation with low spur levels, while the fractional-N synthesizer is added to provide fine frequency resolution through phase interpolation. By combining these two approaches, the system achieves frequency resolution beyond what integer-N alone can provide, while maintaining much of the design simplicity and low spur characteristics of the integer-N approach.
Data Source
AI summary
The disclosed systems, structures, and methods are directed to a low jitter phase-lock loop (PLL) based frequency synthesizer, comprising a first frequency divider, a phase frequency detector, a charge pump, a low-pass filter, a voltage control oscillator (VCO), a phase interpolator communicatively coupled in a feedback path between the VCO and the phase frequency detector, wherein the phase interpolator comprises a quadrature generator, an input conditioner, a phase rotator, a current mode logic (CML), and a second frequency divider communicatively coupled in the feedback path between the phase interpolator and the phase frequency detector.