PLL Phase Interpolator Pairing for Higher Linearity
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Solution Overview
Problem
High-speed network devices face challenges in adjusting for phase skew and phase offsets between clock lanes and data lanes due to systematic non-linearity in phase interpolation, which is exacerbated by high-speed communication requirements and lack of closed-loop clock and data recovery circuitry.
Innovation Solution
A phase-locked loop (PLL) device is employed between feed-forward clock circuitry and sampler circuits, featuring a pair of phase interpolators in a feedback path, where the phases of one PI are shifted relative to the other to maximize integral non-linearity cancellation within an integrator circuit, improving linearity of phase interpolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single phase interpolator is used in the PLL, then the device complexity is reduced, but the linearity of phase interpolation deteriorates due to systematic non-linearity
Solution Approach 1:
The single phase interpolator is segmented into two parallel phase interpolators (first PI and second PI). Each PI handles a different phase relationship (in-phase and quadrature), allowing the system to cancel out systematic non-linearities by combining their outputs. This segmentation resolves the contradiction by distributing the interpolation function across multiple units to achieve better overall linearity.
Solution Approach 2:
An integrator circuit is introduced as an intermediary between the two phase interpolators and the feedback path. This integrator combines the outputs of both PIs in a way that maximizes cancellation of integral non-linearity. The intermediary element enables the system to achieve high linearity without requiring either PI to be perfectly linear on its own.
2Device complexity
If phase skew adjustment is implemented without closed-loop CDR circuitry, then the device complexity is reduced, but the ability to adjust for phase skew and phase offsets deteriorates
Solution Approach 1:
A feedback path is implemented that feeds the combined output of the two phase interpolators back to the phase detectors. This feedback mechanism allows the system to continuously monitor and adjust for phase skew and phase offsets between clock and data lanes. The feedback loop enables adaptive phase alignment without requiring full closed-loop CDR circuitry, resolving the contradiction between simplicity and adaptability.
3Productivity
If high-speed communication is implemented, then the productivity is increased, but the systematic non-linearity in phase interpolation is exacerbated
Solution Approach 1:
The system changes the phase relationship parameter between the two interpolators by introducing a quadrature phase shift (90 degrees) in addition to the in-phase relationship. This parameter change allows the two PIs to operate at different points in the non-linearity cycle, enabling their non-linearities to cancel when combined. This resolves the contradiction by using parameter diversity to mitigate non-linearity effects at high speeds.
Data Source
AI summary
A phase-locked loop (PLL) device includes a first phase detector to receive an in-phase reference clock and an in-phase feedback clock, the first phase detector to output a first phase error; a second phase detector to receive a quadrature reference clock and a quadrature feedback clock, the second phase detector to output a second phase error; a proportional path component to generate first current pulses from the first phase error and second current pulses from the second phase error; an integrator circuit coupled to the proportional path component, the integrator circuit to sum, within a current output signal, the first current pulses and the second current pulses; a ring oscillator to be driven by the current output signal; and a pair of phase interpolators coupled to an output of the ring oscillator, the pair of phase interpolators to respectively generate the in-phase feedback clock and the quadrature feedback clock.