PLL Phase Interpolator Control for Low-Jitter SSC Clocks
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Solution Overview
Problem
In PLL circuits, the jitter of the output clock signal as a spread spectrum clock cannot be sufficiently suppressed due to transient response issues, especially when the phase change amount of the feedback clock is not appropriately controlled, leading to incomplete suppression of jitter in existing SSC generation methods.
Innovation Solution
A PLL circuit is designed with a phase comparing unit, voltage controlled oscillator, phase interpolator, frequency-dividing circuit, and controlling unit that gradually changes the phase shift amount of the phase-shifted signal by a unit of the basic delay amount, ensuring the difference in total phase shift between consecutive periods is equal to or less than one basic delay amount, thereby smoothing the modulation degree and suppressing jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the phase interpolator is arranged on the feedback path to frequency-modulate the VCO output clock signal, then the jitter characteristics of the SSC are improved, but the transient response causes insufficient jitter suppression when phase change amount is not appropriately controlled
Solution Approach 1:
The patent applies dynamics by making the phase shift amount adjustable and variable over time. The controlling unit dynamically changes the phase shift amount of the phase interpolator based on feedback clock signal period variations, allowing the system to adapt to different operating conditions and suppress jitter effectively without causing transient response issues.
Solution Approach 2:
The patent implements feedback control by monitoring the period of the feedback clock signal and adjusting the phase shift amount accordingly. The controlling unit calculates the feedback clock signal period and modifies the phase interpolator's phase shift amount to maintain stable jitter characteristics, creating a closed-loop control system that suppresses transient response effects.
2Adaptability or versatility
If the phase shift amount is changed to adjust SSC modulation degree, then the modulation flexibility is improved, but the transient response of the PLL causes jitter to be insufficiently suppressed
Solution Approach 1:
The patent makes the phase shift amount dynamic and adjustable based on feedback clock signal characteristics. The controlling unit calculates the feedback clock signal period and adjusts the phase shift amount proportionally, enabling flexible SSC modulation while maintaining jitter suppression by adapting to different modulation requirements in real-time.
Solution Approach 2:
The patent changes the phase shift amount parameter dynamically based on the feedback clock signal period. By adjusting this parameter proportionally to the period variations, the system achieves flexible SSC modulation degree control while maintaining stable jitter characteristics through parameter adaptation.
3Adaptability or versatility
If a phase interpolator is used to generate frequency-modulated SSC by advancing or retarding phase, then the SSC generation capability is improved, but high frequency jitter component is superimposed on the SSC
Solution Approach 1:
The patent uses the feedback clock signal period as an intermediary parameter to control the phase shift amount. By calculating the feedback clock signal period and using it to determine the appropriate phase shift amount, the system indirectly controls the phase interpolator, which suppresses high frequency jitter components while maintaining SSC generation capability.
Solution Approach 2:
The patent implements feedback control where the phase shift amount is determined by the feedback clock signal period. This feedback mechanism ensures that phase adjustments are made at appropriate timing and magnitude, preventing high frequency jitter components from being superimposed on the SSC while maintaining effective SSC generation.
Data Source
AI summary
A controlling unit disposed in a PLL circuit controls a phase interpolator to gradually change a phase shift amount applied to a phase shift signal C_PS by a unit of basic delay amount Δ at a timing predetermined in accordance with a modulation profile of an SSC. Further, the controlling unit controls a total phase shift amount applied to the phase shift signal C_PS output from the phase interpolator in one period of a feedback clock signal C_FB obtained by dividing frequency of the phase shift signal C_PS in a way that a difference between the total phase shift amount and a total phase shift amount in a previous one period of C_FB is always equal to or less than the basic delay amount Δ.