PLL Phase Noise Modeling for Accurate Jitter Estimation
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Solution Overview
Problem
Accurate estimation of jitter in Phase-Locked Loops (PLLs) is challenging due to noise associated with their output signals, which can affect the proper operation of integrated circuits, especially when clock signals have varying levels of phase noise.
Innovation Solution
A method is introduced to model phase noise using a single intrinsic phase noise factor and a single gain factor for the PLL, allowing for the prediction of output phase noise based on input noise levels by analyzing the relationship between input and output phase noise through a reference clock signal with varying phase noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If PLL circuitry is used to reduce clock skew in integrated circuits, then synchronization is improved, but phase noise and jitter are introduced in the output signal
Solution Approach 1:
The patent introduces a measurement system that acts as an intermediary between the PLL output and the analysis equipment. This measurement system includes a delay element and a summing junction that combine the PLL output signal with a delayed version of itself, creating a modified signal that can be analyzed to extract phase noise characteristics without directly interfering with the PLL's synchronization function.
Solution Approach 2:
The patent replaces direct observation of phase noise with a mathematical transformation approach. Instead of attempting to measure phase noise directly from the PLL output, the system uses signal processing techniques including delay, summation, and spectral analysis to indirectly determine phase noise characteristics through the relationship between input and output signals.
2Reliability
If accurate jitter estimation is performed to ensure proper component operation, then reliability is improved, but measurement and analysis complexity increases
Solution Approach 1:
The patent employs feedback by measuring the PLL output phase noise and using this information to determine the maximum permissible input phase noise. The measurement results feed back into the design process, allowing engineers to specify appropriate input clock requirements that ensure reliable component operation while accounting for the PLL's noise characteristics.
Solution Approach 2:
The patent performs preliminary characterization of the PLL's phase noise properties during the design phase. By measuring the phase noise transfer function and intrinsic phase noise in advance, the system establishes a model that can predict output jitter for any given input conditions, eliminating the need for complex real-time measurements during operation.
3Measurement precision
If phase noise measurement is performed to predict output jitter, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent segments the phase noise measurement problem into distinct components: the phase noise transfer function (G) and the intrinsic phase noise (Pint). By separating these elements, the measurement system can characterize each independently and combine them to predict total output phase noise, simplifying the overall measurement approach while maintaining precision.
Solution Approach 2:
The patent changes the measurement parameters by working in the frequency domain rather than directly in the time domain. By measuring phase noise spectral density and using spectral analysis techniques, the system achieves precise jitter prediction through mathematical relationships between frequency domain characteristics, avoiding the complexity of direct time-domain jitter measurement.
Data Source
AI summary
A phase-locked loop is characterized by analyzing phase noise in its output signal while known levels of input phase noise are provided. The resulting data provides intrinsic phase noise and gain of the phase-locked loop. These values provide a general relationship between input phase noise and output phase noise for the phase-locked loop, which allows estimation of output phase noise corresponding to a given level of input phase noise, and allows estimation of input phase noise corresponding to a given level of output phase noise.