PLL Phase Modulation for Nonlinear Phase Noise Mitigation
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Solution Overview
Problem
Current wireless communication systems face limitations in speed and throughput due to noise, which causes retransmissions and unreliable communications, and existing techniques struggle to effectively mitigate noise-induced phase errors in digital phase locked loops (DPLLs) and all-digital phase locked loops (ADPLLs).
Innovation Solution
The solution involves modulating the input of a phase difference quantizer in DPLLs or ADPLLs to transform 'bad fractions' into 'good fractions' using a selected modulation scheme, which mitigates spurious contributions to integrated phase noise, and compensating for this modulation digitally using pre-calibrated values before computing the loop phase error.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If digital phase locked loops (DPLLs) or all-digital phase locked loops (ADPLLs) are used to generate clock signals, then integration of wireless communication functions is improved, but nonlinearity related phase noise degradations occur
Solution Approach 1:
The patent applies parameter changes by modifying the fractional frequency value parameter. Specifically, when a bad fraction is detected, the system adjusts the fractional frequency parameter to a nearby good fraction value, thereby transforming the problematic parameter into a beneficial one that reduces phase noise while maintaining functional operation
Solution Approach 2:
The patent implements feedback mechanisms through phase noise measurement and detection circuits that continuously monitor the phase noise characteristics of the DPLL/ADPLL output. Based on the measured phase noise performance, the system provides feedback to adjust the fractional frequency parameter, creating a closed-loop control system that dynamically optimizes phase noise performance
2Adaptability or versatility
If fractional frequency values are used in DPLLs or ADPLLs, then frequency synthesis flexibility is improved, but non-linear phase errors increase due to 'bad fractions' in the feedback signal
Solution Approach 1:
The system dynamically changes the fractional frequency parameter based on its value. When the parameter falls within a bad fraction range, it is adjusted to a nearby good fraction value, thereby maintaining frequency synthesis flexibility while eliminating non-linear phase errors. This selective parameter modification preserves adaptability while improving measurement precision
Solution Approach 2:
The patent converts the harmful effect of bad fractions into a benefit by using the known characteristics of bad fractions to trigger parameter adjustments. The system deliberately modifies the fractional frequency parameter when bad fractions are detected, transforming the problematic condition into an opportunity to optimize phase accuracy while maintaining frequency synthesis capability
Data Source
AI summary
A phase locked loop (PLL) system for mitigating non-linear phase errors stemming from time-variant integral non-linearity of the LO feedback phase quantizer (TDC) is disclosed. The system includes a phase modulation circuit which is configured to generate a plurality of phase shifts for a reference signal; select a phase shift of the plurality of phase shifts and introduce the selected phase shift into the reference signal, thereby modulating the phase difference between the feedback and the reference signal. Alternatively, the above phase modulation can be applied on the feedback signal path, attaining equivalent results. TDC is configured to quantize the phase of the LO feedback signal relative to the shifted reference signal to generate a phase detection signal, effectively modulating the non-linearity contributed error away from the LO center frequency. The phase detection signal is then digitally compensated for the intentional fractional frequency shift to allow the PLL to generate LO signal the desired frequency.