PLL Clock Phase Adjustment for Multi-ADC Radar Synchronization
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Solution Overview
Problem
High-performance automotive radar sensors for autonomous driving face challenges in achieving stringent angular resolution due to timing differences and PCB skew, which introduce errors in signal processing and compromise the accuracy of angular position estimation.
Innovation Solution
A phase-locked loop (PLL) apparatus with adjustable divider circuitry allows for compensation of timing differences by delaying or advancing the output clock signal relative to the feedback clock signal, ensuring phase-coherent ADC clock synchronization across multiple integrated circuits, thereby mitigating PCB skew and improving clock synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the reference clock signal is transmitted between different elements of the apparatus, then clock synchronization is achieved, but timing differences due to PCB skew are introduced
Solution Approach 1:
The patent applies preliminary action by adjusting the phase of the output clock signal before it is used for ADC sampling. The phase adjustment is performed in advance to compensate for the timing delays that will occur during signal transmission, thereby pre-correcting the synchronization issues before they affect measurement precision.
Solution Approach 2:
The patent changes the phase parameter of the output clock signal to compensate for timing differences. By adjusting the phase shift amount, the system optimizes the clock signal timing to counteract PCB skew effects, thereby maintaining both synchronization reliability and measurement precision.
2Measurement precision
If multiple ADCs are used to increase angular resolution, then measurement precision is improved, but clock synchronization becomes more difficult to maintain
Solution Approach 1:
The patent implements a universal phase adjustment mechanism that serves multiple ADC channels simultaneously. The single phase-adjustable output clock signal distribution system provides synchronized clocking to all ADCs, reducing the complexity that would otherwise arise from individually managing synchronization for each ADC channel.
Solution Approach 2:
The patent employs feedback by monitoring the phase coherence of clock signals across multiple ADC channels and adjusting the output clock phase accordingly. This feedback mechanism ensures that all ADCs remain synchronized even as system conditions change, maintaining measurement precision without proportionally increasing synchronization complexity.
3Measurement precision
If the output clock signal is adjusted to compensate for timing delays, then angular position estimation accuracy is improved, but phase coherence may be compromised
Solution Approach 1:
The patent carefully adjusts the phase parameter within optimized ranges that compensate for timing delays while preserving phase coherence. The phase adjustment is designed to correct specific timing offsets without introducing excessive phase shifts that would disrupt the coherent operation of the phased array system.
Solution Approach 2:
The patent applies local phase adjustment to specific clock signal paths where timing delays occur, rather than uniformly adjusting all phases. This localized approach compensates for PCB skew in affected channels while maintaining the overall phase coherence structure of the multi-ADC system.
Data Source
AI summary
There is disclosed an apparatus comprising a first phase-locked loop comprising: a phase detector (302, 304), arranged to receive a reference clock signal (306) and a feedback clock signal (308) and to output a frequency control signal based on a phase difference between the reference clock signal (306) and the feedback clock signal (308); a variable-frequency oscillator (312, 314) arranged to output an oscillator signal having a frequency dependent on said frequency control signal; first divider circuitry (316) for generating said feedback clock signal (308) by frequency-dividing said oscillator signal; and second divider circuitry (320) for generating an output clock signal (3220 by frequency-dividing said oscillator signal; wherein a phase relation between said first divider circuitry (316) and said second divider circuitry (320) is adjustable to delay or advance said output clock signal (322) relative to said feedback clock signal (308). The apparatus may be a radar receiver or transceiver.