PLL Phase Comparator with Reset Current Cancellation
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Solution Overview
Problem
Existing methods for suppressing phase noise in low offset frequency regions within PLL circuits often compromise loop stability, requiring longer noise averaging periods.
Innovation Solution
A phase comparator configuration that includes a phase frequency comparator, a reset pulse simulation circuit, a charge pump circuit, and a current output circuit with switched capacitors, allowing for the generation and averaging of currents based on phase differences and reset signals to reduce noise without affecting loop stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the output current of the charge pump is accumulated and discharged over a plurality of periods to average noise, then phase noise in the low offset frequency region is suppressed, but loop stability is deteriorated
Solution Approach 1:
The patent divides the charge pump output current into two separate paths: one path accumulates current from the main phase comparison output, and another path accumulates current from the reset pulse output. These two accumulated currents are then subtracted to produce the final output. This segmentation allows noise averaging to occur in both paths simultaneously, suppressing phase noise without requiring extension of the accumulation period that would harm loop stability.
Solution Approach 2:
The patent changes the parameter of accumulation period by operating two parallel accumulation circuits with different timing characteristics. The first accumulation circuit processes the main phase comparison current, while the second accumulation circuit processes the reset pulse current. By adjusting the subtraction timing and accumulation durations independently, the system achieves effective noise averaging without extending the overall loop response time, thus maintaining loop stability.
2Manufacturing precision
If a reset pulse signal with certain pulse width is generated even when phase difference is zero, then nonlinearity of phase comparison characteristic is prevented, but noise current is output due to parasitic capacitor charging and discharging
Solution Approach 1:
The patent converts the harmful noise current generated by parasitic capacitor charging/discharging during reset pulses into a beneficial component by routing it through a separate accumulation and subtraction path. The reset pulse-induced noise current is accumulated in a dedicated circuit and then subtracted from the main output, effectively canceling its harmful effect while preserving the necessary reset functionality for maintaining phase comparison linearity.
Solution Approach 2:
The patent extracts the reset pulse signal path from the main phase comparison path, processing them separately through independent accumulation circuits. By separating the reset pulse handling from the main signal path, the system can maintain the necessary reset functionality for linearity while isolating and canceling the noise current it generates through differential subtraction.
Data Source
AI summary
A phase comparator functions to compare phases of a reference clock signal and a feedback clock signal, and output a voltage rising and a voltage falling signals based on a phase difference, to output a rising reset and a falling reset signals having a pulse width of the voltage rising and the voltage falling signals when the phase difference is zero every time the phase frequency comparator outputs the voltage rising and the voltage falling signals, to output a first current based on the voltage rising and the voltage falling signals, and output a second current based on the rising reset and the falling reset signals, and having a capacitor charged with the first current and the second current, to output a current based on a difference between the charges by the first current and the second current.