PLL Feedback Phase Segmentation for Fine Offset and Low Jitter
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Solution Overview
Problem
Dynamic divider PLL devices face issues with phase noise and jitter due to changes in division ratios, causing quantization noise that is difficult to mitigate, especially in high-performance applications where precise phase control is required.
Innovation Solution
The implementation of a feedback portion with multiple instances of phase and frequency detectors and charge pumps, along with a multiplex network, allows for finer temporal resolution of phase changes within one clock cycle, reducing quantization noise by generating multiple feedback clock signals that collectively provide feedback for phase/frequency comparison.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dynamic division ratios are used in PLL devices, then frequency tuning range and adaptability are improved, but phase noise and jitter increase due to quantization noise
Solution Approach 1:
The feedback path is segmented into multiple parallel PFD/CP instances, each operating at different phase offsets. This segmentation allows the system to achieve fine phase control by selecting from multiple discrete phase samples, reducing quantization noise while maintaining dynamic division ratios for frequency tuning.
Solution Approach 2:
The invention adds a phase dimension to the feedback mechanism by creating multiple feedback paths with different phase offsets. This transforms the single-dimensional frequency control into a multi-dimensional control space, enabling independent optimization of phase noise and frequency tuning range.
2Measurement precision
If multiple feedback paths are implemented, then phase control precision is improved, but device complexity increases
Solution Approach 1:
Each additional PFD/CP instance serves multiple functions: it provides phase sampling for fine control, contributes to the overall feedback signal, and enables dynamic phase adjustment. This multi-functionality reduces the relative complexity overhead of adding multiple feedback paths.
Solution Approach 2:
The multiple PFD/CP instances are nested within a unified feedback architecture controlled by a single phase/frequency control engine. This nested structure allows shared control logic and resource utilization, reducing the complexity increase from multiple feedback paths.
Data Source
AI summary
Implementations provide a phase locked loop (PLL) device that includes: a phase and frequency detector (PFD) and charge pump (CP) portion; a low pass filter; a voltage controlled oscillator (VCO) driven by the low pass filter to generate a VCO clock signal, multiple divider configured to receive the VCO clock signal and frequency divide the VCO clock signal in stages to generate a series statically divided VCO clock signals and a dynamically divided VCO clock signal; a feedback portion including a first component configured to receive the dynamically divided VCO clock signal and generate indicator signals; and a second component configured to multiplex from the indicator signals to generate the feedback clock signal set for the PFD and CP portion; and a master phase/frequency control engine configured to assert a division control over at least one divider and a multiplex control over the multiplex network.