PLL Frequency Synthesizer with Phase-Selector Pre-Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing PLL frequency synthesizers face limitations in achieving small channel spacings, particularly in Bluetooth and other short-range radio data communication protocols, due to the constraints of integer N PLLs and the increased power consumption and bandwidth limitations of fractional N PLLs, which are not adequately addressed by current technologies.
Innovation Solution
A phase locked loop frequency synthesizer with a voltage-controlled oscillator operating at a multiple of the target frequency, utilizing a pre-scaler with a second frequency divider and phase selector arrangement to alter the phase of the output frequency, reducing quantization noise and allowing for finer frequency adjustments without the need for additional high-frequency dividers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a lower reference frequency is used to achieve smaller channel spacings, then channel spacing resolution is improved, but loop bandwidth is limited and power consumption increases
Solution Approach 1:
The frequency division function is segmented into two independent dividers operating at different frequencies. The first divider operates at the high VCO frequency to provide coarse division, while the second divider operates at the lower output frequency to provide fine frequency adjustment. This segmentation allows the system to achieve small channel spacings without using a low reference frequency, thereby avoiding the associated power consumption and bandwidth limitations.
2Measurement precision
If a high frequency divider is added to achieve finer frequency adjustments, then frequency control precision is improved, but device complexity increases
Solution Approach 1:
The second frequency divider is designed to be universal by receiving its input from the output of the first divider rather than requiring a separate high-frequency signal path. This multi-functional approach allows the same divider circuitry to serve both frequency division and fine frequency adjustment functions, avoiding the need for additional high-frequency dividers and reducing overall device complexity.
3Object-affected harmful factors
If the VCO operates at a multiple of the target frequency, then quantization noise is reduced, but additional frequency division is required
Solution Approach 1:
The system performs preliminary frequency division by operating the VCO at a multiple of the target frequency and using the first frequency divider to reduce the frequency before it reaches the second divider. This preliminary action reduces the quantization noise impact on the final output while the phase selector arrangement ensures that the additional division stages do not significantly increase device complexity.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A phase locked loop frequency synthesizer is arranged to provide a target frequency output signal for a radio transmitter or receiver. The synthesizer comprises: a voltage controlled oscillator (2) operating at a first frequency; a first, fixed frequency divider (8) arranged to provide a first output (10, 12) at a second frequency, wherein said second frequency is a fixed fraction of said first frequency; a pre-scaler arranged to provide a variable frequency division of said second frequency to produce a third frequency, said pre-scaler comprising: a second frequency divider (14) connected to said first output (12) and providing a second output at a second frequency; and a phase selector arrangement (16) arranged selectively to alter a phase of said second output in order to alter said second frequency; a frequency controller (20) controlling said pre-scaler and thereby controlling said third frequency; and a phase detector (4) controlling said voltage controlled oscillator (2) on the basis of a comparison between a reference signal and a signal dependent on said third frequency; wherein the synthesizer is configured so that said first output (10, 12) provides said target frequency output signal.