PLL Phase Synchronization Circuit for Fractional-N Locking
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Solution Overview
Problem
Fractional-N phase-locked loops (PLLs) in RF communication systems face challenges in synchronizing the phase of their output clock signals with a reference clock signal, leading to unpredictable locking and difficulty in measuring input and output phases due to sigma-delta noise and quantization, which is crucial for maintaining phase relationships in multi-PLL systems and frequency hopping applications.
Innovation Solution
A phase synchronization circuit is introduced that includes a sampling circuit, phase difference calculation circuit, and phase adjustment control circuit to synchronize the PLL's phase by generating samples based on the reference clock, calculating phase differences, and providing adjustments to maintain lock and synchronize multiple PLLs across transceiver chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If fractional-N PLL is used to provide finer output frequency adjustment steps, then frequency tuning resolution is improved, but phase synchronization with reference clock becomes unpredictable and difficult to measure
Solution Approach 1:
The patent implements a feedback mechanism where the phase synchronization circuit continuously monitors the PLL output phase and compares it with the reference clock phase. The measured phase difference is fed back to adjust the fractional division value dynamically, ensuring reliable phase synchronization while maintaining fine frequency resolution. This closed-loop control resolves the contradiction by making phase synchronization predictable despite using fractional division.
Solution Approach 2:
The patent replaces direct phase measurement methods with a statistical approach using autocorrelation analysis of sampled signals. Instead of directly measuring phase (which is corrupted by sigma-delta noise), the system samples the PLL output over multiple cycles and uses signal processing to extract phase information. This substitution of measurement methodology enables accurate phase synchronization in fractional-N PLLs.
2Manufacturing precision
If sigma-delta modulation is used in fractional-N PLL to achieve fine frequency steps, then frequency resolution is improved, but phase measurement becomes difficult due to noise and quantization
Solution Approach 1:
The patent introduces an intermediary sampling circuit that captures PLL output signals at multiple time points without directly measuring the corrupted phase signal. By sampling at intermediate points and using autocorrelation processing, the system indirectly extracts accurate phase information. This intermediary approach bypasses the noise and quantization issues inherent in direct phase measurement of sigma-delta modulated signals.
Solution Approach 2:
The patent creates multiple copies of the PLL output signal through sampling and processes these copies statistically. By generating multiple signal copies and analyzing their autocorrelation properties, the system derives phase information that is not directly observable in any single corrupted signal instance. This copying and statistical analysis approach overcomes the measurement difficulties caused by sigma-delta noise.
3Productivity
If multiple PLLs are used in multi-PLL systems for massive MIMO, then system capacity is improved, but maintaining phase relationships across all PLLs becomes complex
Solution Approach 1:
The patent implements a universal phase synchronization circuit that can be applied to any number of PLLs in the system. Each PLL is equipped with an identical synchronization module that independently measures and corrects its phase relationship with the reference clock. This universal approach allows arbitrary numbers of PLLs to be synchronized without increasing overall system complexity, as each unit operates autonomously using the same methodology.
Data Source
Figure 1A~1B
Figure 2
Figure 3A
AI summary
Apparatus and methods for phase synchronization of phase-locked loops (PLLs) are provided. In certain configurations, an RF communication system includes a PLL that generates one or more output clock signals and a phase synchronization circuit that synchronizes a phase of the PLL. The phase synchronization circuit includes a sampling circuit that generates samples by sampling the one or more output clock signals based on timing of a reference clock signal. Additionally, the phase synchronization circuit includes a phase difference calculation circuit that generates a phase difference signal based on the samples and a tracking digital phase signal representing the phase of the PLL. The phase synchronization circuit further includes a phase adjustment control circuit that provides a phase adjustment to the PLL based on the phase difference signal so as to synchronize the PLL.