PLL Circuit Phase Synchronization for Time-to-Digital Conversion Accuracy
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Solution Overview
Problem
Existing time-to-digital conversion technologies face challenges in accuracy and complexity due to the need for synchronization point detection between clock pulses, difficulty in handling frequency mismatches, and errors in edge matching detection, leading to increased conversion time and reduced accuracy.
Innovation Solution
A circuit device employing a PLL circuit for phase synchronization between two clock signals of different frequencies, allowing for immediate conversion without waiting for synchronization point detection and enabling accurate conversion even with frequency mismatches, by using resonators to generate clock signals and adjusting frequencies for precise phase alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If edge matching detection is used to detect synchronization point between clock pulses, then time-to-digital conversion can be performed, but conversion time increases and accuracy deteriorates due to detection errors
Solution Approach 1:
The PLL circuit performs preliminary phase synchronization between the first and second clock signals before the time-to-digital conversion process begins. This preliminary action ensures that the clock signals are already synchronized, eliminating the need for real-time edge matching detection during conversion, thus reducing conversion time and improving accuracy.
Solution Approach 2:
The PLL circuit acts as an intermediary between the two clock signals, mediating their phase relationship. By introducing this intermediate synchronization mechanism, the system achieves accurate phase alignment without requiring direct edge matching detection between the clock pulses, thereby reducing both conversion time and detection errors.
2Measurement precision
If synchronization point detection is required before time measurement, then accurate time-to-digital conversion can be achieved, but the conversion process becomes complicated and conversion time increases
Solution Approach 1:
The PLL circuit performs self-service phase synchronization by automatically adjusting the phase of one clock signal relative to the other. This self-synchronizing mechanism eliminates the need for complex external synchronization point detection circuits, simplifying the overall conversion process while maintaining accuracy.
Solution Approach 2:
The PLL circuit employs feedback control to continuously monitor and adjust the phase relationship between clock signals. This feedback mechanism automatically maintains synchronization without requiring complex detection logic, thereby reducing process complexity while ensuring accurate time-to-digital conversion.
3Measurement precision
If frequency relationship between clock pulses does not allow edge coincidence at synchronization point, then time-to-digital conversion becomes difficult to realize, but using resonators with different frequencies provides better resolution
Solution Approach 1:
The system changes the frequency parameters of the clock signals by using resonators with different frequencies. The PLL circuit compensates for these frequency differences through phase adjustment, allowing the system to maintain synchronization capability while achieving better time measurement resolution through the frequency difference between resonators.
Data Source
AI summary
A circuit device includes a time-to-digital conversion circuit, to which a first clock signal generated using a first resonator, and having a first clock frequency, and a second clock signal generated using a second resonator, and having a second clock frequency different from the first clock frequency are input, and which converts time into a digital value using the first and second clock signals, and a PLL circuit adapted to perform phase synchronization between the first and second clock signals.