PLL Phase-Error Window Tracking for FMCW Radar Lock Detection
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Solution Overview
Problem
Phase-error tracking in phase locked loop (PLL) circuit implementations for applications like automotive radar systems faces inefficiencies due to challenges in aligning reference and feedback signal phases, particularly in frequency-modulated continuous wave (FMCW) systems.
Innovation Solution
A phase-error tracking circuit that defines a phase-error window based on the slope of the frequency range change, indicating whether a phase error between the divider feedback signal and the reference signal coincides with this window, ensuring the PLL circuit maintains phase lock and is insensitive to duty cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase locked loop (PLL) circuit is used to align reference phase and feedback signal phase, then phase lock is achieved, but the alignment occurs around an arbitrary value reducing tracking efficiency
Solution Approach 1:
The patent applies preliminary action by pre-defining a desired phase-lock value before the PLL operation begins. The phase error tracking circuit is configured with this predetermined value, allowing the system to proactively guide the phase alignment process toward the correct target rather than allowing arbitrary alignment. This resolves the contradiction by maintaining reliable phase lock while improving tracking efficiency through directed alignment.
Solution Approach 2:
The patent changes the parameter reference by introducing a desired phase-lock value as a new reference point for phase comparison. Instead of accepting arbitrary phase alignment, the system modifies the tracking criterion to reference this specific desired value. This parameter change enables the PLL to maintain stable lock while efficiently tracking phase errors relative to the correct alignment target.
2Adaptability or versatility
If phase error tracking is implemented in FMCW radar systems, then radar signal generation is enabled, but inefficiencies occur due to arbitrary phase alignment values
Solution Approach 1:
The patent applies preliminary action by pre-configuring the phase error tracking circuit with a desired phase-lock value specific to FMCW radar requirements. This predetermined reference value is established before radar signal generation begins, ensuring that the phase tracking is directed toward the correct alignment target. This resolves the efficiency problem while maintaining the adaptability needed for FMCW radar operation.
Solution Approach 2:
The patent changes the tracking parameter from arbitrary phase alignment to alignment relative to a desired phase-lock value. This parameter modification is specifically tailored for FMCW radar applications, where the desired phase-lock value corresponds to the correct frequency modulation characteristics. This enables efficient phase error tracking while maintaining the versatility required for radar signal generation.
3Measurement precision
If the phase-error window is defined based on slope sensing, then lock detection accuracy is improved, but circuit complexity increases
Solution Approach 1:
The patent introduces a slope sensing mechanism as an intermediary element that bridges the phase error signal and the phase-error window definition. Rather than directly comparing phases, the slope of the phase error signal is sensed and used to dynamically adjust the window boundaries. This intermediary approach improves lock detection accuracy by accounting for the rate of phase change, while the implementation remains integrated within the existing PLL architecture, limiting the increase in circuit complexity.
Data Source
AI summary
Embodiments are directed to apparatuses and methods involving a phase-error tracking circuit. An example apparatus includes a divide-by phase locked loop (PLL) circuit to generate a continuous wave signal that sweeps over a frequency range in response to a divider feedback signal and to a reference signal. The apparatus further includes the phase-error tracking circuit defining a phase-error window in which the divide-by PLL circuit is to lock based on a slope associated with a rate of change of the frequency range, and indicating whether a phase error between the divider feedback signal and the reference signal coincides with the phase-error window.