Adaptive PLL Loop Filter Reset Using Power-Gated Pulse Control
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Solution Overview
Problem
Conventional phase lock loops (PLLs) with sample-reset loop filters (SR-LFs) consume excessive power due to inefficient reset circuits, which are costly and wasteful, especially at varying output frequencies, leading to stability issues and increased power consumption without enhancing PLL performance.
Innovation Solution
A power gating pulse circuit is introduced to generate adaptive reset control signals with significantly shorter pulse widths, based on phase errors and switch control signals, to efficiently reset capacitors in the PLL's proportional path, reducing power consumption and maintaining stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional reset circuits are used in the sample-reset loop filter, then the capacitors are reset to avoid memory effect and maintain PLL stability, but the power consumption increases significantly and manufacturing cost rises
Solution Approach 1:
The patent implements periodic resetting of the loop filter capacitors at specific intervals (e.g., every N reference cycles) rather than continuous or frequent resetting. The reset controller activates the reset circuit only when needed based on detected phase error conditions, creating a periodic action pattern that maintains stability while reducing power consumption by keeping the reset circuit inactive during normal operation
Solution Approach 2:
The patent changes the reset parameter from frequent/continuous resetting to conditional/interval-based resetting. The reset controller monitors phase error and only triggers reset when specific conditions are met, dynamically adjusting the reset frequency and timing parameters to optimize between stability maintenance and power consumption reduction
2Reliability
If reset circuits with precision resistors are used, then the loop filter can effectively reset capacitors, but the manufacturing cost and device footprint increase
Solution Approach 1:
The patent extracts and removes the expensive precision resistors from the reset circuit design. The reset functionality is achieved through alternative means (reset controller with conditional logic and standard components) that eliminate the need for high-precision passive components, thereby reducing manufacturing cost and simplifying the bill of materials while maintaining reset effectiveness
Solution Approach 2:
The patent replaces expensive, precision-critical components (precision resistors) with cheaper, more readily available standard components. The reset circuit uses conventional resistors and active components controlled by a reset controller, substituting high-cost precision parts with lower-cost alternatives that achieve the same functional result without requiring tight tolerances
3Stability of the object's composition
If continuous reset signals are applied to the loop filter, then capacitor memory effect is prevented, but power consumption increases and lock time may be extended
Solution Approach 1:
The patent applies periodic reset signals only when phase error conditions are detected, rather than continuous reset signals. The reset controller monitors the phase detector output and triggers reset periodically or conditionally, maintaining phase margin by preventing memory effect only when necessary, thereby avoiding unnecessary extension of lock time during normal locked operation
Solution Approach 2:
The patent applies reset action preliminarily or preventively only when phase error conditions indicate potential instability. The reset controller detects early signs of phase error accumulation and triggers reset before significant memory effect occurs, maintaining stability proactively while avoiding continuous resetting that would extend lock time during normal operation
Data Source
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AI summary
An apparatus has a phase lock loop with an adaptive loop filter that has a reset circuit controlled by a power gating pulse circuit.