PLL Supply Pre-Boost for Frequency Overshoot and Voltage Droop

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Solution Overview

Problem

Phase locked loops (PLLs) experience frequency overshoot when correcting phase or frequency changes, leading to increased supply voltage guard bands, which negatively impact system performance and limit the effectiveness of adaptive frequency scaling techniques.

Innovation Solution

An apparatus that temporarily boosts the supply voltage before a potential frequency overshoot event, allowing the PLL to lock quickly without long-term voltage guard bands, and reduces the voltage back to the expected level, thereby absorbing the overshoot impact.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If the PLL is overdamped to mitigate frequency overshoot, then frequency stability is improved, but lock/relock time increases significantly

Engineering Contradiction:
Improvefrequency stabilityVSAvoidlock/relock time
Core Design Contradiction:
Stability of the object's compositionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by detecting voltage droop conditions before they cause frequency overshoot and proactively adjusting the PLL parameters or supply voltage. The droop detector circuit monitors voltage conditions and triggers preventive measures (such as adjusting damping factors or voltage levels) before the frequency overshoot occurs, thus maintaining frequency stability without requiring excessive damping that would slow down lock/relock times.

Inventive Principle:
Principle #10Preliminary action

2Stability of the object's composition

If supply voltage guard bands are increased to absorb frequency overshoot, then frequency stability is improved, but system performance decreases and minimum operating voltage increases

Engineering Contradiction:
Improvefrequency stabilityVSAvoidsystem performance
Core Design Contradiction:
Stability of the object's compositionVSProductivity

Solution Approach 1:

The patent detects voltage droop conditions in advance and triggers preventive voltage adjustments before frequency overshoot occurs. By proactively managing voltage levels based on detected droop conditions, the system maintains frequency stability without needing to permanently increase supply voltage guard bands, thus preserving system performance and keeping minimum operating voltage requirements low.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system uses self-service by implementing an automatic droop detection and response mechanism that operates without external intervention. The droop detector circuit continuously monitors voltage conditions and automatically triggers corrective actions (such as adjusting PLL parameters or supply voltage) when droop is detected, enabling the system to self-correct frequency stability issues without impacting overall performance.

Inventive Principle:
Principle #25Self-service

3Productivity

If adaptive frequency scaling is used to improve performance, then productivity is improved, but frequency overshoot occurs during transitions

Engineering Contradiction:
Improveprocessing speedVSAvoidfrequency stability
Core Design Contradiction:
ProductivityVSStability of the object's composition

Solution Approach 1:

The patent implements feedback by using a droop detector circuit that continuously monitors supply voltage conditions during AFS transitions. When voltage droop is detected, the system receives feedback and automatically adjusts PLL parameters or voltage levels to prevent frequency overshoot. This closed-loop feedback mechanism enables aggressive AFS transitions to improve performance while maintaining frequency stability through real-time corrections.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10928886B2Frequency overshoot and voltage droop mitigation apparatus and method
Publication Date: 2021.02.23 INTEL CORP
  • US10928886B2 patent drawing
  • US10928886B2 patent drawing
  • US10928886B2 patent drawing

AI summary

An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocking source, such as a phase locked loop (PLL) to lock fast while not needing any long-term voltage guard bands. The apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on Vmin During the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. Such boost allows for absorbing the clock frequency overshoot impact. The supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.