Phase-Locked Loop Averaging for Pulse-Gap Signal Tracking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional phase locked loops (PLLs) with input signals containing gaps in pulse sequences suffer from poor tracking performance due to the need to reduce loop bandwidth to filter out phase jumps, leading to increased costs and power consumption from requiring large buffer capacities.
Innovation Solution
A phase locked loop design that includes a first and second frequency divider, and a calculation unit to calculate and average phase differences between signals from these dividers, allowing improved tracking performance without reducing the loop bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the loop bandwidth is reduced to filter out phase jumps from pulse gaps, then the PLL can handle signals with gaps, but the tracking performance to changes in input signal deteriorates
Solution Approach 1:
The patent segments the phase difference calculation into multiple discrete phase points within one cycle of the output signal from the first frequency divider. By calculating phase differences at multiple points and averaging them, the system can filter out phase jumps from pulse gaps while maintaining good tracking performance, resolving the contradiction between reliability and speed.
2Stability of the object's composition
If the loop bandwidth is reduced to filter out phase jumps, then phase stability improves, but the response time to input signal changes increases
Solution Approach 1:
The patent implements a feedback mechanism where the calculated average phase difference is fed back to adjust the output signal. By continuously calculating phase differences at multiple points and averaging them, the system achieves both phase stability and fast response time, resolving the contradiction between stability and time loss.
3Measurement precision
If large buffer capacities are used to maintain tracking performance, then tracking accuracy improves, but power consumption and cost increase
Solution Approach 1:
The patent changes the parameter of phase difference calculation from a single point to multiple points within one cycle. This parameter change enables the system to achieve high tracking accuracy through calculation rather than requiring large buffer capacities, thereby reducing power consumption and cost while maintaining tracking precision.
Data Source
AI summary
In a phase locked loop, a first frequency divider divides the frequency of an input signal. A low-pass filter receives a frequency-divided signal output from the first frequency divider and having an average phase difference calculated by a calculation unit, cuts off high-frequency components of the received signal, and outputs a resultant signal. A voltage controlled oscillator varies the frequency of a signal to be output based on the signal output from the low-pass filter. A second frequency divider divides the frequency of the signal output from the voltage controlled oscillator. The calculation unit calculates a phase difference between signals individually output from the first frequency divider and the second frequency divider for each phase in one cycle of the signal output from the first frequency divider, and calculates an average phase difference based on the calculated phase differences.