PLL Pulse Limiter for Adaptive Pulse Truncation
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Solution Overview
Problem
Phase locked loops (PLLs) configured for low gain operational environments to combat transient noise during clock switch-over events are more susceptible to noise and errors, and existing truncation systems are complex and prone to transistor mismatch, leading to inefficiencies and reliability issues in clock synchronization.
Innovation Solution
A pulse limiter circuit that truncates INC and DEC pulses based on a delay buffer selection, determining if the pulse width exceeds the minimum pulse width plus a delay period, allowing for adaptive gain operation and reducing the number of delay elements, thereby minimizing noise susceptibility and transistor mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the PLL is configured for low gain operation to combat transient noise, then noise susceptibility is reduced, but the PLL becomes more susceptible to noise and errors
Solution Approach 1:
The pulse limiter dynamically adjusts the gain of the PLL by truncating pulses based on real-time conditions. During transient events, the pulse limiter actively reduces pulse width to lower gain, while during normal operation it allows full pulse width for optimal performance. This dynamic adjustment resolves the contradiction by enabling the system to adapt its noise handling characteristics rather than being fixed in low gain mode.
Solution Approach 2:
The invention changes the effective gain parameter of the PLL by controlling pulse width. The pulse limiter modifies the pulse width parameter dynamically - truncating pulses during transients to reduce gain effects, while maintaining full width during stable operation. This parameter control allows the system to combat transient noise without being permanently configured for low gain, thereby maintaining reliability.
2Device complexity
If existing truncation systems use multiple delay elements to achieve pulse truncation, then truncation functionality is provided, but the system becomes complex and prone to transistor mismatch
Solution Approach 1:
The pulse limiter combines multiple delay elements into a single integrated delay block with a unified delay value. Instead of using separate delay elements that can exhibit transistor mismatch, the invention merges them into one cohesive unit that applies a consistent delay to all pulses. This merging eliminates the transistor mismatch problem while maintaining the necessary truncation functionality, directly resolving the contradiction between complexity and reliability.
Solution Approach 2:
The delay block is segmented into multiple selectable delay stages, allowing the system to achieve variable truncation levels without requiring multiple complete sets of delay elements. This segmentation approach reduces the total number of delay elements needed while maintaining functionality, thereby reducing both complexity and the potential for transistor mismatch.
Data Source
AI summary
A phase locked loop includes a pulse limiter between a phase frequency detector and a charge pump. The phase frequency detector generates and sends a clock pulse to the pulse limiter. The pulse limiter generates a first signal that indicates that the clock pulse is greater than a minimum pulse width of the phase frequency detector. The pulse limiter receives a pulse limiter buffer selection signal that selects one buffer of a plurality of buffers within the pulse limiter. The pulse limiter generates a second signal that indicates a truncated pulse width as the minimum pulse width of the phase frequency detector plus a delay period that is associated with the pulse limiter buffer selection signal. The pulse limiter truncates the clock pulse to the truncated pulse width and sends the truncated clock pulse to the charge pump.