PLL Charge Pump Pulse Limiting for Low-Jitter Locking
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Solution Overview
Problem
Phase-locked loop (PLL) circuits face issues with high jitter and noise in the voltage controlled oscillator (VCO) control voltage due to uncontrolled charge pump current pulses, especially with high phase offsets or missing clock pulses, which conventional methods cannot adequately address by reducing loop filter bandwidth.
Innovation Solution
A PLL circuit with a phase frequency detector and charge pump that limits the duration of charge and discharge current pulses using pulse duration detection circuitry, including XOR-gates and OR-gates, to prevent excessive voltage changes and noise, and disables the charge pump when pulse durations exceed a predetermined value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the loop filter bandwidth is reduced to reduce charge pump noise, then noise performance improves, but acquisition time increases and responsiveness decreases
Solution Approach 1:
The patent implements dynamic bandwidth control by switching between two loop filter configurations: a first loop filter with higher bandwidth for fast acquisition, and a second loop filter with lower bandwidth for low noise operation. The system automatically transitions between these states based on lock detection, resolving the contradiction between fast acquisition and low noise performance.
Solution Approach 2:
The patent employs periodic switching between high-bandwidth and low-bandwidth modes based on PLL lock status. During acquisition, the high-bandwidth mode enables rapid locking; after lock is achieved, the system switches to low-bandwidth mode for reduced noise, creating a time-periodic behavior that optimizes both acquisition speed and noise performance at different operational phases.
2Reliability
If the charge pump current pulse width is increased to reduce output jitter, then frequency stability improves, but voltage control instability increases due to excessive voltage changes
Solution Approach 1:
The patent changes the loop filter bandwidth parameter dynamically based on operational phase. By adjusting this key parameter, the system can accommodate different charge pump pulse widths appropriately - allowing wider pulses during acquisition without excessive voltage changes, while maintaining stability during locked operation with narrower pulses.
3Object-affected harmful factors
If the PLL bandwidth is reduced to filter noise, then noise performance improves, but the ability to track frequency changes decreases
Solution Approach 1:
The patent implements dynamic bandwidth adjustment by switching between two loop filters with different bandwidth characteristics. The first loop filter provides high bandwidth for fast frequency tracking during acquisition, while the second loop filter provides low bandwidth for superior noise filtering during locked operation, resolving the contradiction between tracking speed and noise rejection.
Data Source
AI summary
A phase-locked loop circuit comprises a phase frequency detector, a charge pump associated with a loop capacitance, and a voltage controlled oscillator. The phase frequency detector receives a reference clock signal on a first input and a feedback signal from the voltage controlled oscillator on a second input. The charge pump receives control inputs from outputs of the phase frequency detector. Pulse duration detecting circuitry limits charge and discharge current pulses supplied to the loop capacitance by the charge pump to durations less than predetermined permissible durations.