PLL Pulse Multiplication for Higher Phase Information Bandwidth
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Solution Overview
Problem
In phase-locked loops (PLLs), the low response bandwidth due to infrequent phase events in the reference input signal compared to the output signal limits the control loop's effectiveness in applications like frequency synthesis and clock recovery.
Innovation Solution
A phase-locked loop configuration that includes a phase-frequency detector and a pulse multiplier, which duplicates and offsets digital pulses to increase the phase information bandwidth without modifying other components, thereby enhancing the proportional gain of the feedback loop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phase-frequency detector compares reference signal to feedback signal with infrequent phase events, then the PLL can operate with standard component values, but the response bandwidth is limited and proportional gain is reduced
Solution Approach 1:
The pulse multiplier creates multiple copies of the phase detector output pulses. By duplicating the phase information N times, the effective proportional gain is increased by a factor of N without requiring changes to the physical components like VCO capacitance or supply voltage. This copying approach directly resolves the contradiction by maintaining reliable operation with standard components while achieving higher bandwidth through increased proportional gain.
2Device complexity
If phase-frequency detector output is used directly without multiplication, then the device complexity is low, but the proportional gain of the feedback loop is insufficient for high bandwidth applications
Solution Approach 1:
The pulse multiplier segments the phase information into multiple identical pulse trains. By dividing the single phase detector output into N separate copies, each carrying the same phase information, the system achieves higher effective proportional gain while adding minimal complexity. The segmentation allows the existing phase detector to operate at its natural frequency while the multiplied outputs provide the enhanced gain needed for high bandwidth applications.
3Productivity
If the reference signal has infrequent phase events compared to the output signal frequency, then the PLL can maintain frequency multiplication capability, but the control loop response becomes slow and bandwidth is reduced
Solution Approach 1:
The pulse multiplier applies periodic duplication to the phase detector outputs, creating N periodic pulse trains from each phase event. This periodic multiplication effectively increases the rate at which phase information is processed by the loop filter and charge pump, reducing the loop response time by a factor of N while preserving the frequency multiplication capability derived from the reference signal's phase events.
Data Source
AI summary
A phase-locked loop (PLL) includes a phase-frequency detector that compares a reference signal to a feedback signal. The difference in phase between the reference signal and the feedback signal is encoded as digital pulses on one or more outputs of the phase-frequency detector. The digital output pulses from the phase-frequency detector are duplicated and delayed multiple times in a non-overlapping manner before being input to the loop filter or voltage controlled oscillator (VCO) of the PLL.