Ultra-Low Bandwidth PLL Control Stage With PVT Compensation
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Solution Overview
Problem
Existing ultra-low bandwidth phase locked loops (PLLs) require large external components and high power consumption, which is not suitable for handheld and mobile devices that need to minimize chip area and power usage while reducing the number of external components.
Innovation Solution
A low-bandwidth PLL design using only two storage cells and a digital-to-analog (DAC) converter, along with an improved process-voltage-temperature (PVT) compensation technique that adjusts the charge pump current based on the VCO's output current, and reducing frequency peaking by increasing the time to charge or discharge storage cell capacitors using a high-speed clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional ultra-low bandwidth PLL design is used, then low bandwidth is achieved, but large external components and high power consumption are required
Solution Approach 1:
The patent replaces the traditional analog loop filter with a semi-digital control stage comprising storage cells and a DAC converter. This substitution eliminates the need for large external capacitors while achieving the same low bandwidth effect through digital storage elements that integrate directly on-chip, thereby reducing both external component requirements and power consumption.
Solution Approach 2:
The patent changes the operating parameters by using a high-speed clock signal (e.g., 1 GHz) with a reduced duty cycle (e.g., 20%) to charge and discharge the storage cell capacitors. This parameter change allows the capacitors to be much smaller in size while still achieving the required time constants for ultra-low bandwidth operation, directly addressing both the component size and power consumption issues.
2Speed
If traditional ultra-low bandwidth PLL design is used, then low bandwidth is achieved, but chip area increases due to large external components
Solution Approach 1:
The patent replaces the traditional analog loop filter with a semi-digital control stage comprising storage cells and a DAC converter. This substitution eliminates the need for large external capacitors while achieving the same low bandwidth effect through digital storage elements that integrate directly on-chip, thereby reducing both external component requirements and power consumption.
Solution Approach 2:
The patent changes the operating parameters by using a high-speed clock signal (e.g., 1 GHz) with a reduced duty cycle (e.g., 20%) to charge and discharge the storage cell capacitors. This parameter change allows the capacitors to be much smaller in size while still achieving the required time constants for ultra-low bandwidth operation, directly addressing both the component size and power consumption issues.
3Reliability
If traditional PLL design is used, then frequency peaking occurs in the frequency response, but settling response can be improved by reducing peaking
Solution Approach 1:
The patent changes the operating parameters by using a high-speed clock signal with a reduced duty cycle (e.g., 20%) to charge and discharge the storage cell capacitors. This parameter change effectively reduces the integral gain in the feedback loop, which suppresses frequency peaking in the frequency response while maintaining fast settling performance through the high clock frequency.
Data Source
AI summary
The invention generally relates to phase locked loops (PLL), and more specifically to ultra-low bandwidth phase locked loops. The invention may be for example embodied in an integrated circuit implementing a phase locked loop or a method for operating a phase locked loop. The invention provides a PLL with a control stage that uses only two storage cells, a counter and a digital-to-analog (DAC) converter. In comparison to prior-art PLLs using storage cells the configuration of the invention's control stage reduces the chip area required for the PLL reduced. The invention further suggests PVT compensation mechanisms for a PLL and implementing a PLL that has lower peaking in its frequency response, which results in better settling response.