PLL Random Number Generator Uniform Distribution and Power Reduction
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Solution Overview
Problem
Existing PLL-based random number generators suffer from non-uniform statistical distribution, fixed rate data stream instability, and metastability issues, making them unsuitable for cryptology applications and requiring high power consumption due to high clock frequencies.
Innovation Solution
The implementation of a modified PLL circuit with a dead band time delay, swapping of random and reference clock inputs, and an additional synchronization flip-flop to achieve a uniform distribution, constant frequency rate, and prevent metastability, respectively, while using a standard PLL with high noise content and reduced clock frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high clock frequencies are used to generate random numbers, then the bit rate of the random number sequence is improved, but the power consumption increases
Solution Approach 1:
The patent changes the operating parameters by using a standard PLL circuit operating at lower clock frequencies (e.g., 40 MHz reference clock) rather than requiring high frequency clocks. The invention achieves high bit rate output by using a multiplication ratio of one and directly sampling the VCO output at the reference clock frequency, eliminating the need for high frequency operation while maintaining high productivity
2Device complexity
If a standard PLL circuit is used without modifications, then the device complexity is reduced, but the output distribution becomes non-uniform and skewed
Solution Approach 1:
The patent extracts only the essential noise-generating component (VCO) from the PLL circuit and uses it directly for random number generation. By taking out the VCO output and sampling it with a simple D flip-flop clocked by the reference clock, the invention achieves uniform distribution without requiring complex modifications to the entire PLL circuit, thus maintaining low device complexity while improving output uniformity
3Device complexity
If the PLL output is sampled directly without additional circuitry, then the device complexity is minimized, but metastability conditions occur and the data stream becomes unstable
Solution Approach 1:
The patent introduces a D flip-flop as an intermediary element between the VCO output and the final output. This flip-flop is clocked by the reference clock and samples the VCO output at precise intervals, acting as a mediator that resolves metastability issues. The intermediary synchronizes the random signal with the reference clock, ensuring stable data stream output without requiring complex synchronization circuitry
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in a stable, uniformly distributed random number generator with reduced power consumption, capable of generating high bit rates at reference clock frequencies, suitable for cryptology applications.
Implementation Method 1
the VCO frequency output is configured to contain high noise content
Data Source
AI summary
An improved bit rate efficient random number generators (RNG) based on a phase lock loop (PLL) circuit is described. The invention is configured to provide a high quality random number statistical distribution at the reference clock rate. This ability to create a random serial data stream at the reference clock rate eliminates high frequency clocks required by other RNG implementations thereby reducing power consumption. The random sequence serial data stream allows a unique random number to be generated each reference clock cycle by accumulation into an N-Bit shift register. Example schematics and performance simulations are presented to establish numerical statistics.