PLL Rational Division Decomposition for Low-Spur Frequency Synthesis
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Solution Overview
Problem
Conventional fractional-N frequency synthesizers face challenges due to inherent fractional spurs caused by low resolution in the feedback path, leading to PLL frequency jitter and limitations in resolving large numerator and denominator values, especially in modern communication systems that require multiple synthesized frequencies from a single reference clock.
Innovation Solution
The system employs a flexible accumulator that allows true rational number division, decomposing numerator and denominator into sub-divisors when bit resolution is exceeded, and uses complementing functions to reduce bit resolution, enabling low resolution rational division decomposition in the feedback path of the PLL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional fractional-N frequency synthesizers use fractional number decimal values in their PLL architectures, then frequency synthesis is achieved, but inherent fractional spurs are generated due to lack of resolution in the feedback path
Solution Approach 1:
The feedback path is segmented into multiple parallel paths: an integer division path and a fractional accumulation path. The integer path uses a simple integer divider while the fractional path uses accumulators to generate correction terms. This segmentation allows the system to achieve high frequency resolution through the fractional path without introducing spurs in the integer path, as each path operates independently with appropriate resolution.
Solution Approach 2:
Accumulators are introduced as intermediary components in the feedback path to handle fractional division. These accumulators convert fractional division operations into integer addition operations, allowing precise fractional frequency synthesis without directly introducing fractional spurs. The accumulators act as mediators that translate the fractional frequency requirement into a form that can be processed by integer-based digital logic without generating harmful spectral components.
2Measurement precision
If high bit resolution is used to resolve large numerator and denominator values in rational division, then frequency synthesis accuracy is improved, but device complexity and resource requirements increase
Solution Approach 1:
The rational division operation is segmented into integer and fractional parts. The integer part is handled by a simple integer divider requiring minimal bit resolution, while the fractional part is handled by accumulators that process the remainder. This segmentation allows the system to achieve high frequency synthesis accuracy without requiring the entire system to operate at high bit resolution, reducing overall device complexity.
Solution Approach 2:
The system dynamically changes the parameter of division type based on the input frequencies. When the frequency ratio can be represented as an integer, integer division is used with low bit resolution. When fractional precision is needed, the system switches to fractional division mode using accumulators, adjusting the effective bit resolution only where necessary to maintain accuracy while minimizing complexity.
3Adaptability or versatility
If a single reference clock frequency is used to generate multiple synthesized frequencies, then system adaptability is improved, but frequency resolution and accuracy may deteriorate
Solution Approach 1:
The feedback path is designed with universal components that can handle both integer and fractional division operations. The same accumulator-based fractional division mechanism works for all frequency synthesis requirements regardless of the target frequency, providing a unified solution that maintains high resolution across multiple frequency generations from a single reference clock.
Solution Approach 2:
The system dynamically adjusts the division ratio parameters (numerator and denominator values) based on the desired output frequency while maintaining a fixed reference clock. The fractional accumulation path adapts its operation to provide the necessary frequency resolution for each synthesized frequency, allowing the system to maintain high precision across multiple frequency points without changing the reference clock architecture.
Data Source
AI summary
A method is provided for synthesizing signal frequencies using low resolution rational division decomposition in a frequency synthesis device. An integer numerator (n) and an integer denominator (d) ratio is reduced; n/d=IO(NO/DO)=IO+NO/DO=(IO+1)−(DO−NO)/DO, and where NO/DO<1 and NO and DO are integers. NO is reduced; NO=In(Nn/Dn)=In+Nn/Dn=(In+1)−(Dn−Nn)/Dn, where In, Nn, and Dn are integers, and Nn/Dn<1. In, Nn, and Dn are used to create a final numerator divisor. DO is reduced; DO=Id(Nd/Dd)=Id+Nd/Dd=(Id+1)−(Dd−Nd)/Dd, where Id, Nd, and Dd are integers, and Nd/Dd<1. Id, Nd, and Dd are used to create a final denominator divisor. Finally, IO, the final numerator divisor, and the final denominator divisor are used to create a final divisor.