PLL Clock Test Logic Using Reference Counting Without IO Pads
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Solution Overview
Problem
The increasing complexity of System-on-Chips (SoCs) with multiple embedded Phase-Locked Loops (PLLs) necessitates new testing architectures to accurately monitor PLL clock frequencies and lock signals without propagating signals through device input/output pads, which can lead to reduced accuracy due to signal allocation and routing issues.
Innovation Solution
A system and method for testing PLLs that includes a phase-locked loop, a test logic circuit coupled to the PLL, and a test controller, which uses a reference clock to count clock cycles and measure clock frequency, allowing direct monitoring of PLL signals without routing through IO pads, and utilizing standard interfaces like IEEE 1149.1 for control and monitoring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If signals are propagated through device input/output pads for PLL testing, then testing can be performed using external equipment, but measurement accuracy is reduced due to signal allocation and routing issues
Solution Approach 1:
The patent extracts the PLL testing function from external equipment and implements it within the device using internal test logic circuits. These circuits directly access PLL signals inside the device, eliminating the need to route signals through IO pads and thereby removing the source of measurement inaccuracies while reducing signal routing complexity.
Solution Approach 2:
The patent introduces test logic circuits as intermediary components that interface between the PLL and the testing mechanism. These circuits provide direct access to PLL signals internally, serving as mediators that enable accurate measurement without requiring external signal routing through IO pads.
2Productivity
If multiple PLLs are tested using traditional architectures, then comprehensive testing coverage is achieved, but test time increases and parallel execution is limited
Solution Approach 1:
The patent segments the testing function by providing dedicated test logic circuits for each PLL, allowing independent and parallel operation. This segmentation enables multiple PLLs to be tested simultaneously without interference, reducing total test time while maintaining manageable architecture through modular organization.
Solution Approach 2:
The patent creates universal test logic circuits that can function with multiple different PLLs using the same testing methodology. These circuits provide multi-functional capability to test various PLL configurations and frequencies, enabling comprehensive testing coverage across multiple devices without increasing architectural complexity.
3Ease of manufacture
If complex signal routing is used to access PLL signals for testing, then external testing equipment can be connected, but testing costs and architectural complexity increase
Solution Approach 1:
The patent implements self-service testing where the device contains its own test logic circuits that can autonomously test the PLL functionality. This eliminates the need for complex external signal routing and specialized testing equipment, thereby reducing manufacturing and testing costs while simplifying the overall architecture.
Solution Approach 2:
The patent merges the testing functionality with the existing device architecture by integrating test logic circuits within the same device. This consolidation eliminates the need for separate external testing infrastructure and complex signal routing, reducing both architectural complexity and testing costs.
Data Source
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AI summary
A system for testing a circuit includes a phase-locked loop (200), a test logic circuit (400, 500, 600, 700), and a test controller (300). The test logic circuit is coupled to the phase-locked loop. The test logic circuit (400, 500, 600, 700) is configured to count a number of clock cycles of the phase-locked loop (200) using a reference clock (414) as a reference. The reference clock (414) is coupled to the test logic circuit (400, 500, 600, 700). The test controller (300) is coupled to the phase-locked loop (200) and to the test logic circuit (400, 500, 600, 700). The test controller (300) is configured to measure a clock frequency of the phase-locked loop with the counted number of clock cycles received from the test logic circuit (400).